W89C840F
The following figures describe the chain structures of receive descriptor.
first descritpor of the RX descriptor
status register
structure constructing register
data buffer 1 pointer
data buffer 1
data buffer 1
data buffer 1
for storing the first RX packet data
for storing the 2nd RX packet data
for storing the 3rd RX packet data
next descriptor pointer
second descritpor of the RX descriptor
status register
structure constructing register
data buffer 1 pointer
next descriptor pointer
third descritpor of the RX descriptor
status register
structure constructing register
data buffer 1 pointer
next descriptor pointer
last descritpor of the RX descriptor
status register
structure constructing register
data buffer 1 pointer
data buffer 1
for storing the nth RX packet data
next descriptor pointer
As shown in the above diagram, all descriptors are linked by pointers to construct a chain. The data
can be stored in more than one data buffers. In the last descriptor of the descriptor chain, the content of the
R03 register will be ignored by the receive DMA state machine if the RLINK bit of the R01 register in the
last descriptor is set to high. When the last descriptor has already been used, the next descriptor pointer in
this one will link to the start address of the first descriptor in the chain if it is available.
In the chain structure, the base address of the first descriptors is specified by the C0C/CRDLA
register, the receiving descriptors list address register and the base address of the next descriptor is pointed
by the R03 of the current descriptor.
The following figure describes the mixed mode list, composed of both the ring and the chain
structures at the same time.
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ETC [ ETC ]
