W89C840F
SERRB
O/OD
System Error:
This pin will be asserted with one PCI clock width
within two PCI clocks after an address parity error is
detected and keep in high impedance state when idle.
The interrupt function caused by this event is gated by
the bits in FCS register.
The W89C840F will assert SERRB and set a high to the
Detect Parity Error bit FCS<31>, the Signal System
Erro bit FCS<30> if an error, address parity error, is
detected and SERRB enable bit FCS<8> is previously
set to 1.
The Bus Error Status bit C14<13> will be set to high if
an address parity error is detected and the parity error
response bit FCS<6> is set to high.
INTAB
O/OD
Interrupt A:
INTAB is asserted when any of the unmasked interrupt
bits in C14/CISR are set. It will be kept asserted until all
of the unmasked interrupt bits are cleared.
2) BootROM and EEPROM Interface
Signal Name
Pin Type Pin
Number
Pin Description
BtAdd0
BtAdd1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
BootROM address bit 0
BootROM address bit 1
BtAdata[7:4]
BtAdata[3]/EEDO
BtAdata[2]/EEDI
BtAdata[1]/EECK
BtAdata[0]
BootROM address and data bus: bit7 - bit4.
EEPROM data output; BootROM address &data:bit3
EEPROM data input; BootROM address & data:bit2.
EEPROM data clock; BootROM address & data:bit1.
BootROM address & data:bit0
BtCSB
BootROM chip select
EECS
EEPROM chip select
3) MII Interface
Signal Name
Pin
Pin
Pin Description
Type Number
- 8 -
ETC [ ETC ]
