Microelectronics
Inc.
BRIGHT
BM29F400T/BM29F400B
PIN CONFIGURATIONS
PIN DESCRIPTION
A0−A17
DQ0−DQ14
DQ15/A-1
CE
OE
WE
V
SS
RESET
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE
RESET
NC
NC
RY/BY
NC
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
BYTE
Vss
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
Vcc
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE
Vss
CE
A0
Standard TSOP
RY/BY
V
CC
BYTE
NC
Address Inputs
Data Input/Output
Data Input/Output, Address
Max.
Chip Enable
Output Enable
Write Enable
Device Ground
Hardware RESET Pin,
Active Low
Ready/Busy Status Output
Device Power Supply
Selects 8-bit or 16-bit Mode
Not Internally Connected
BLOCK DIAGRAM
Vcc
Vss
/WE
/BYTE
/RESET
RY/BY
Buffer
State
Control
Command
Register
DQ0-DQ15
Erase Boltage
Generator
Input/Output
Buffers
PGM Voltage
Generator
Chip Enable
Output Enable
Logic
STB
Data Latch
/CE
/OE
STB
Y-Decodor
Vcc Detector
A0-A16
A-1
Address
Latch
X-Decoder
Y-Gating
Cell Matrix
Timer
A Winbond Company
-3-
Publication Release Date: December 1999
Revision A2
WINBOND [ WINBOND ]
