BRIGHT
Microelectronics
Inc.
BM29F400T/BM29F400B
PIN CONFIGURATIONS
PIN DESCRIPTION
Address Inputs
Data Input/Output
Data Input/Output, Address
Max.
-
A0 A17
DQ0- DQ14
DQ15/A-1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
1
A15
A14
A13
A12
A11
A10
A9
BYTE
Vss
2
3
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
Vcc
4
5
Chip Enable
CE
OE
WE
6
7
8
A8
Output Enable
Write Enable
Device Ground
9
NC
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
WE
RESET
NC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE
NC
SS
V
RY/BY
NC
A17
A7
RESET
RESET
Hardware Pin,
Active Low
A6
A5
A4
Vss
A3
CE
A2
RY/BY
CC
Ready/Busy Status Output
Device Power Supply
A0
A1
V
Standard TSOP
Selects 8-bit or 16-bit Mode
BYTE
NC
Not Internally Connected
BLOCK DIAGRAM
DQ0-DQ15
Vcc
Vss
RY/BY
Buffer
Erase Boltage
Generator
Input/Output
Buffers
State
Control
/WE
/BYTE
/RESET
Command
Register
PGM Voltage
Generator
STB
Chip Enable
Output Enable
Logic
/CE
/OE
Data Latch
STB
Y-Gating
Y-Decodor
Cell Matrix
Vcc Detector
Address
Latch
Timer
X-Decoder
A0-A16
A-1
A Winbond Company
Publication Release Date: December 1999
Revision A2
- 3 -
WINBOND [ WINBOND ]
