73S8004R
Low Cost Smart Card Interface
CMDVCC
VCC
I/O
CLK
RSTIN
RST
t1
t3
t4
t2
Figure 2: Activation Sequence – Timing Diagram #1
t1 = 0.510 ms (timing by 1.5MHz internal Oscillator)
t2 = 1.5µs, I/O goes to reception state
t3 = >0.5µs, CLK starts
t4 = 42000 card clock cycles. Time for RST to become the copy of RSTIN
The following steps show the activation sequence and the timing of the card control signals when the system
controller pulls the CMDVCC low while the RSTIN is high:
-
-
CMDVCC is asserted low.
Next, the internal VCC control circuit checks the presence of VCC during t1. In normal operation, the
voltage VCC to the card becomes valid during this time. If not, OFF goes low to report a fault to the
system controller, and the power VCC to the card is de-asserted.
-
-
-
Turn I/O (AUX1, AUX2) to reception mode at the end of (t2) due to fall of RSTIN.
CLK is applied to the card at the end of (t3).
RST is to be a copy of RSTIN after (t4). If RSTIN is high prior to t4, RST will de-assert at t4.
CMDVCC
VCC
I/O
CLK
RSTIN
RST
t3
t1
t2
t4
Figure 3: Activation Sequence – Timing Diagram #2
t1 = 0.510 ms (timing by 1.5MHz internal Oscillator)
t2 = 1.5µs, I/O goes to reception state
t3 = > 0.5µs, CLK active
t4 = 42000 card clock cycles. Time for RST to become the copy of RSTIN
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© 2002-2003 TDK Semiconductor Corporation
Proprietary and Confidential
Rev 1.1
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
