欢迎访问ic37.com |
会员登录 免费注册
发布采购

73S8004R-ILF 参数 Datasheet PDF下载

73S8004R-ILF图片预览
型号: 73S8004R-ILF
PDF下载: 下载PDF文件 查看货源
内容描述: [Microprocessor Circuit, PDSO28,]
分类和应用: 光电二极管外围集成电路
文件页数/大小: 18 页 / 298 K
品牌: TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
 浏览型号73S8004R-ILF的Datasheet PDF文件第2页浏览型号73S8004R-ILF的Datasheet PDF文件第3页浏览型号73S8004R-ILF的Datasheet PDF文件第4页浏览型号73S8004R-ILF的Datasheet PDF文件第5页浏览型号73S8004R-ILF的Datasheet PDF文件第7页浏览型号73S8004R-ILF的Datasheet PDF文件第8页浏览型号73S8004R-ILF的Datasheet PDF文件第9页浏览型号73S8004R-ILF的Datasheet PDF文件第10页  
73S8004R  
Low Cost Smart Card Interface  
OVER-TEMPERATURE MONITOR  
A built-in detector monitors die temperature. Upon a over-temperature condition, a card deactivation sequence is  
initiated, and an error or fault condition is reported to the system controller.  
CARD CLOCK  
Internal clock circuitry generates the card clock from the crystal oscillator when a crystal is connected, or from the  
clock externally applied on the pin XTALIN. The card clock frequency may be chosen between 4 different division  
rates, defined by digital inputs CLKDIV 1 and CLKDIV 2, as per the following table:  
CLKDIV1  
CLKDIV2  
CLK  
0
0
1
1
0
1
0
1
1/8 XTALIN  
¼ XTALIN  
XTALIN  
½ XTALIN  
Card power down mode (card clock STOP) is supported and is controllable through the dedicated digital inputs  
CLKSTOP and CLKLEV.  
ACTIVATION SEQUENCE  
The TDK 73S8004R smart card interface IC has an internal 10ms delay at power on reset or on the application of  
VDD > VDDF. No activation is allowed at this time. The CMDVCC (edge triggered) must then be asserted low to  
activate the card. In order to initiate activation, the card must be present, there can be no over-temperature fault  
or no VDD fault.  
The following steps show the activation sequence and the timing of the card control signals when the system  
controller asserts the CMDVCC low while the RSTIN is low:  
-
-
CMDVCC is asserted low.  
Next, the internal VCC control circuit checks the presence of VCC during t1. In normal operation, the  
voltage VCC to the card becomes valid during t1. If VCC does not become valid, the OFF goes low to  
report a fault to the system controller, and the power VCC to the card is de-asserted.  
Turn I/O (AUX1, AUX2) to reception mode at the end of (t2).  
-
-
-
CLK is applied to the card at the end of (t3).  
RST is a copy of RSTIN after (t4). RSTIN may be set high before t4 to automatically de-assert RST  
42000 clock cycles after the start of CLK.  
Page 6  
© 2002-2003 TDK Semiconductor Corporation  
Proprietary and Confidential  
Rev 1.1