73S8004R
Low Cost Smart Card Interface
MICROCONTROLLER INTERFACE
PIN
NAME
DESCRIPTION
(SO)
Command VCC (negative assertion): Logic low on this pin causes the LDO regulator to ramp
the VCC supply to the card and initiates a card activation sequence, if a card is present.
CMDVCC
19
5 volt / 3 volt card selection: Logic one selects 5 volts for VCC and card interface, logic low
selects 3 volt operation. When the part is to be used with a single card voltage, this pin should
be tied to either GND or VDD. However, it includes a high impedance pull-up resistor to default
this pin high (selection of 5V card) when not connected.
5V/#V
3
Stops the card clock signal during a card session when asserted (card clock STOP mode).
Internal pull-down resistor allows this pin to be left as an open circuit if the clock STOP mode is
not used.
CLKSTOP
CLKLVL
7
8
Sets the logic level of the card clock STOP mode when the clock is de-activated by assertion of
the pin 7. Logic low selects card STOP low. Logic high selects card STOP high. Internal pull-
down resistor allows this pin to be left as an open circuit if the clock STOP mode is not used.
CLKDIV1
CLKDIV2
Sets the divide ratio from the XTAL oscillator (or external clock input) to the card clock. These
pins include pull-down resistors.
CLKDIV1
CLKDIV2
CLOCK RATE
XTALIN/8
XTALIN/4
XTALIN/2
XTALIN
1
2
0
0
1
1
0
1
1
0
Interrupt signal to the processor. Active Low - Multi-function indicating fault conditions and card
OFF
23
presence. Open drain output configuration – It includes an internal 22kΩ pull-up to VDD.
RSTIN
20
26
27
28
Reset Input: This signal is the reset command to the card.
I/OUC
System controller data I/O to/from the card. Includes a pull-up resistor to VDD.
System controller auxiliary data I/O to/from the card. Includes a pull-up resistor to VDD.
System controller auxiliary data I/O to/from the card. Includes a pull-up resistor to VDD.
AUX1UC
AUX2UC
SYSTEM CONTROLLER INTERFACE
ꢁ
ꢁ
ꢁ
3 separated digital inputs allow direct control of the card interface from the host as follows:
ꢁ
ꢁ
ꢁ
Pin CMDVCC: When low, starts an activation sequence
Pin RST: controls the card Reset signal (when enabled by the sequencer)
Pin 5V/#V: Defines the card voltage
Card clock is controlled by 4 digital inputs:
ꢁ
CLKDIV1 and CLKDIV2 define the division rate for the clock frequency, from the input
clock frequency (crystal or external clock)
ꢁ
ꢁ
CLKSTOP (active high) allows card power down mode by stopping the card clock
CLKLEV defines the card clock level of the card power down mode.
Interrupt output to the host: As long as the card is not activated, the OFF pin informs the host
about the card presence only (Low = No card in the reader). When CMDVCC is asserted Low
(Card activation sequence requested from the host), Low level on OFF means a fault has been
detected (e.g. card removal during card session, or voltage fault, or thermal / over-current fault)
that automatically initiates a deactivation sequence.
Page 4
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Proprietary and Confidential
Rev 1.1
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
