73S8004R
Low Cost Smart Card Interface
DEACTIVATION SEQUENCE
Deactivation is initiated either by the system controller by setting the CMDVCC high, or automatically in the event
of hardware faults. Hardware faults are over-current, overheating, VDD fault, VPC fault, VCC fault, and card
extraction during the session. To be noted that VPC and VCC faults are linked together so that a fault is generated
when VPC goes lower than VCC.
The following steps show the deactivation sequence and the timing of the card control signals when the system
controller sets the CMDVCC high:
-
-
-
-
RST goes low at the end of time t1.
De-assert CLK at the end of time t2.
I/O goes low at the end of time t3. Out of reception mode.
VCC is turned off at the end of time t4. After a delay t5 (discharge of the VCC capacitor), VCC is low.
CMDVCC
RST
CLK
I/O
VCC
t1
t2
t3
t4
t5
Figure 4: Deactivation Sequence – Timing Diagram #1
t1 = > 0.5µs, timing by 1.5MHZ internal Oscillator
t2 = > 7.5µs
t3 = > 0.5µs
t4 = > 0.5µs
t5 = depends on VCC filter capacitor. CF=1µF makes t1 + t2 + t3 + t4 + t5 < 100µs
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© 2002-2003 TDK Semiconductor Corporation
Proprietary and Confidential
Rev 1.1
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