Data Sheet 71M6531D/F-71M6532D/F
FDS 6531/6532 005
It is practical to pre-erase pages, disable interrupts and poll the CE_BUSY interrupt flag, IRCON[2]. This
method avoids problems with interrupt latency, but can still result in a write failure if the CE code takes to
much time. As mentioned above, polling FWCOL0 and FWCOL1 can detect write failures. However, the
speed in a polling write is only 2520 bytes per second and the firmware cannot respond to interrupts.
As an alternative to using flash, a small EEPROM can store data without compromises. EEPROM inter-
faces are included in the device.
Updating Individual Bytes in Flash Memory
The original state of a flash byte is 0xFF (all ones). Once a value other than 0xFF is written to a flash
memory cell, overwriting with a different value usually requires that the cell be erased first. Since cells
cannot be erased individually, the page has to be copied to RAM, followed by a page erase. After this,
the page can be updated in RAM and then written back to the flash memory.
Flash Erase Procedures
Flash erasure is initiated by writing a specific data pattern to specific SFR registers in the proper sequence.
These special pattern/sequence requirements prevent inadvertent erasure of the flash memory.
The mass erase sequence is:
1. Write 1 to the FLSH_MEEN bit (SFR address 0xB2[1].
2. Write pattern 0xAA to FLSH_ERASE (SFR address 0x94).
The mass erase cycle can only be initiated when the ICE port is enabled.
The page erase sequence is:
1. Write the page address to FLSH_PGADR (SFR address 0xB7[7:1].
2. Write pattern 0x55 to FLSH_ERASE (SFR address 0x94).
Bank-Switching:
The program memory of the 71M6531 consists of a fixed lower bank of 32 KB addressable at 0x0000 to
0x7FFF plus an upper bank area of 32 KB, addressable at 0x8000 to 0xFFFF. The upper 32 KB space is
banked using the I/O RAM FL_BANK register as follows:
•
•
The 71M6531D provides 4 banks of 32 KB each selected by FL_BANK[1:0]. Note that when
FL_BANK[1:0] = 00, the upper bank is the same as the lower bank.
The 71M6531F and 71M6532D/F provide 8 banks of 32 KB each selected by FL_BANK[2:0].
Table 38 illustrates the bank switching mechanism.
Table 38: Bank Switching with FL_BANK[2:0]
FL_BANK Address Range for Lower
Address Range for Upper
Bank (0x8000-0xFFFF)
Available for Available for
[1:0] / [2:0]
Bank (0x000-0x7FFF)
0x0000-0x7FFF
0x0000-0x7FFF
0x0000-0x7FFF
0x0000-0x7FFF
0x0000-0x7FFF
0x0000-0x7FFF
0x0000-0x7FFF
0x0000-0x7FFF
71M653XD
71M6531XF
000
0x0000-0x7FFF
0x8000-0xFFFF
X
X
X
X
X
X
X
X
X
X
X
X
001
010
0x10000-0x17FFF
0x18000-0x1FFFF
0x20000-0x217FF
0x28000-0x2FFFF
0x30000-0x37FFF
0x38000-0x3FFFF
011
100
101
110
111
Program Security
When enabled, the security feature limits the ICE to global flash erase operations only. All other ICE op-
erations are blocked. This guarantees the security of the user’s MPU and CE program code. Security
40
© 2005-2009 TERIDIAN Semiconductor Corporation
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