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71M6532F 参数 Datasheet PDF下载

71M6532F图片预览
型号: 71M6532F
PDF下载: 下载PDF文件 查看货源
内容描述: 电能计量IC [Energy Meter IC]
分类和应用:
文件页数/大小: 115 页 / 2363 K
品牌: TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
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Data Sheet 71M6531D/F-71M6532D/F  
FDS 6531/6532 005  
Priority  
Assignment  
Interrupt Enable  
Individual Flags  
Individual  
Enable Bits  
Logic and Polarity  
Selection  
Interrupt  
Flags  
Internal  
Source  
External  
Source  
No.  
0
IEN0.0  
(EX0)  
IEN0.7  
(EAL)  
DIO status  
changed  
I T 0  
DIO  
D I O _ R n  
T C O N . 1 ( I E 0 )  
IP1.0/  
IP0.0  
IEN2.0  
(ES1)  
byte received  
S 1 C O N . 0 ( R I 1 )  
S 1 C O N . 1 ( T I 1 )  
UART1  
(optical)  
> = 1  
byte transmitted  
IEN0.1  
(ET0)  
overflow occurred  
T C O N . 5 ( T F 0 )  
SPI_FLAG  
Timer 0  
IEN1.1  
(EX2)  
IP1.1/  
IP0.1  
SPI I/F  
IEN_SPI  
IRCON.1  
(IEX2)  
I 2 F R  
> = 1  
Write attempt, CE  
busy  
Flash  
Write  
Collision  
IEN0.2  
(EX1)  
2
IE_FWCOL0  
IE_FWCOL1  
EX_FWCOL  
D I O _ R n  
CE code start,  
flash write busy  
IEN1.2  
(EX3)  
IP1.2/  
IP0.2  
DIO status  
changed  
1
3
DIO  
T C O N . 3 ( I E 1 )  
IRCON.2  
(IEX3)  
I 3 F R  
CE completed code run and  
has new status information  
CE_BUSY  
P
o
l
l
i
n
g
S
e
q
u
e
n
c
e
IEN0.3  
(ET1)  
overflow occurred  
Timer 1  
T C O N . 7 ( T F 1 )  
IP1.3/  
IP0.3  
IEN1.3  
(EX4)  
IE_PLLRISE  
IE_PLLFALL  
PLL status  
EX_PLL  
IRCON.3  
(IEX4)  
4
PLL OK  
> = 1  
changed  
IEN0.4  
(ES0)  
byte received  
S 0 C O N . 0 ( R I 0 )  
S 0 C O N . 0 ( T I 0 )  
IE_EEX  
UART0  
> = 1  
> = 1  
byte transmitted  
IP1.4/  
IP0.4  
IEN1.4  
(EX5)  
BUSY fell  
IRCON.4  
(IEX5)  
EX_EEX  
EEPROM  
I2C  
5
6
command  
EX_SPI  
IE_SPI  
received  
IP1.5/  
IP0.5  
IEN1.5  
(EX6)  
accumulation  
EX_XFER  
XFER_BUSY  
IE_XFER  
cycle completed  
IRCON.5  
(IEX6)  
every second  
IE_RTC  
> = 1  
EX_RTC  
RTC_1S  
NR_OVF  
WDT near  
overflow  
IEN_NR_  
WDOVF  
WD_NROVF_FLAG  
Flag=1 means  
that an inter-  
rupt has oc-  
curred and  
has not been  
cleared  
EX0  
EX6 are cleared  
automatically when the  
hardware vectors to the  
interrupt handler  
Interrupt  
Vector  
MPU-external  
sources  
MPU-internal  
sources  
2 / 2 /2 0 0 9  
Figure 8: Interrupt Structure  
36  
© 2005-2009 TERIDIAN Semiconductor Corporation  
v1.2  
 
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