FDS 6531/6532 005
Data Sheet 71M6531D/F-71M6532D/F
1.5
On-Chip Resources
1.5.1 Oscillator
The oscillator of the 71M6531D/F and 71M6532D/F drives a standard 32.768 kHz watch crystal. These
crystals are accurate and do not require a high-current oscillator circuit. The oscillator of the 71M6531D/F
and 71M6532D/F has been designed specifically to handle these crystals and is compatible with their
high impedance and limited power handling capability.
Oscillator calibration can improve the accuracy of both the RTC and metering. Refer to Section
1.5.3 Real-Time Clock (RTC) for more information.
The oscillator is powered directly and only from VBAT, which therefore must be connected to a DC vol-
tage source. The oscillator requires approximately 100 nA, which is negligible compared to the internal
leakage of a battery.
The oscillator may appear to work when VBAT is not connected, but this mode of operation is not re-
commended.
If VBAT is connected to a drained battery or disconnected, a battery test that sets BME may drain
VBAT’s supply and cause the oscillator to stop. A stopped oscillator may force the device to reset.
Therefore, an unexpected reset during a battery test should be interpreted as a battery failure.
1.5.2 Internal Clocks
Timing for the device is derived from the 32.768 kHz crystal oscillator output. On-chip timing functions
include:
•
•
•
•
•
The MPU clock (CKMPU)
The emulator clock (2 x CKMPU)
The clock for the CE (CKCE)
The clock driving the delta-sigma ADC along with the FIR (CKADC, CKFIR)
A real time clock (RTC).
The two general-purpose counter/timers contained in the MPU are controlled by CKMPU (see Section
1.4.7 Timers and Counters). Table 37 provides a summary of the available clock functions.
Table 37: Clock System Summary
MCK Divider / [M40MHZ, M26MHZ]
Derived
From
Brownout
Mode
Clock
CKPLL
÷2 / [1,0]
80 MHz
40 MHz
5 MHz † 10 MHz † 6.6 MHz
÷3 / [0,1]
80 MHz
26 MHz
÷4** / [0,0]
80 MHz
20 MHz
5 MHz
Crystal
off
MCK
CKPLL
MCK
112 kHz
off
CKCE
CKADC / CKFIR
MCK
5 MHz
6.6 MHz
6.6 MHz ***
32 kHz
5 MHz
28 kHz
28 kHz
CKMPU maximum MCK
CK32 MCK
** Default state at power-up
10 MHz***
32 kHz
5 MHz ***
32 kHz
*** This is the maximum CKMPU frequency. CKMPU can be reduced from this rate using MPU_DIV.
† CKCE = 10 MHz when CE10MHZ is set, 5 MHz otherwise.
The master clock, MCK, is generated by an on-chip PLL that multiplies the oscillator output frequency
(CK32) by 2400 to provide 80 MHz (78.6432 MHz). A divider controlled by the I/O RAM registers
M40MHZ and M26MHZ permits scaling of MCK by ½, ⅓ and ¼. All other clocks are derived from this
scaled MCK output (making them multiples of 32768 Hz), and the clock skew is matched so that the rising
edges of CKADC, CKCE, CK32 and CKMPU are aligned.
The PLL generates a 2x emulator clock which is controlled by ECK_DIS. Since clock noise from this fea-
ture may disturb the ADC, it is recommended that this option be avoided when possible.
v1.2
© 2005-2009 TERIDIAN Semiconductor Corporation
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