FDS 6531/6532 005
Data Sheet 71M6531D/F-71M6532D/F
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
DIO
17
37
13
5
28 29
48 49
47 24
LCD Segment
Pin number
0
1
Configuration (DIO
or LCD segment)
LCD_MAP[39:32]
LCD_MAP[55:48]
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
1
1
4
5
Data Register
DIO2 = P2 (SFR 0xA0)
DIO3 = P3 (SFR 0xB0)
–
–
–
–
–
Direction Register
0 = input, 1 = output
DIO_DIR2 (SFR 0xA1)
–
–
–
–
–
–
–
DIO
43 44 45 46
63 64 65 66
–
–
–
–
–
–
–
–
LCD Segment
Pin number
29 23 28
5
7
0
1
2
–
Configuration (DIO
or LCD segment)
LCD_BITMAP[63:56] LCD_BITMAP[64:71]
–
–
–
–
–
–
–
–
Data Register
Direction Register
0 = input, 1 = output
1.5.8 Digital I/O – 71M6532D/F
The 71M6532D/F includes up to 43 pins of general-purpose digital I/O. These pins are compatible with 5-
V inputs (no current limiting resistors are needed). The Digital I/O pins can be categorized as follows:
• Dedicated DIO pins (4 pins):
o
DIO3
o
DIO56 – DIO58 (3 pins)
• DIO/LCD segment pins (a total of 37 pins):
o
o
o
o
DIO4/SEG24 – DIO27/SEG47 (24 pins)
DIO29/SEG49, DIO30/SEG50 (2 pins)
DIO40/SEG60 – DIO45/SEG65 (6 pins)
DIO47/SEG67 – DIO51/SEG71 (5 pins)
• DIO pins combined with other functions (2 pins): DIO2/OPT_TX, DIO1/OPT_RX
On reset or power-up, all DIO pins are inputs until they are configured for the desired direction under
MPU control. The pin function can be configured by the I/O RAM registers LCD_BITMAPn. Setting
v1.2
© 2005-2009 TERIDIAN Semiconductor Corporation
43
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
