Data Sheet 71M6531D/F-71M6532D/F
FDS 6531/6532 005
LCD_BITMAPn = 1 configures the pin for LCD, setting LCD_BITMAPn = 0 configures it for DIO. Once a
pin is configured as DIO, it can be configured independently as an input or output with the DIO_DIR bits
or the LCD_SEGn registers. Input and output data are written to or read from the pins using SFR registers
P0, P1, and P2. Table 40 shows all the DIO pins with their configuration, direction control and data regis-
ters.
Table 40: Data/Direction Registers and Internal Resources for DIO Pins (71M6532D/F)
DIO
PB
–
1
–
2
–
3
3
–
4
5
6
7
8
9
10 11 12 13 14 15
LCD Segment
Pin number
24
25 26 27 28 29 30 31 32 33 34 35
100
92
87
17 60
61 62 63 67 68 69 70
44 29 30
0
1
2
3
4
5
6
7
0
1
2
3
Configuration (DIO or
LCD segment)
Always DIO
LCD_BITMAP[31:24]
LCD_BITMAP[39:32]
0
–
1
1
2
3
4
5
6
6
7
7
0
0
1
1
2
3
4
5
6
6
7
7
Data Register
DIO0 = P0 (SFR 0x80)
DIO1 = P1 (SFR 0x90)
2
3
4
5
2
3
4
5
Direction Register
0 = input, 1 = output
DIO_DIR0 (SFR 0xA2)
DIO_DIR1 (SFR 0x91)
Internal Resources
Configurable
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
–
–
–
–
DIO
16
36
33
4
17 18 19 20
37 18 39 40
12 13 64 65
21 22 23 24 25 26 27
41 42 43 44 45 46 47
66 93 54 46 43 42 41
--
--
--
--
29 30
49 50
32 35
--
--
LCD Segment
Pin number
5
6
7
0
1
2
3
--
--
--
--
1
2
--
Configuration (DIO or
LCD segment)
LCD_BITMAP[39:32]
LCD_BITMAP[47:40]
LCD_BITMAP[55:48]
--
0
1
2
3
4
5
6
–
7
0
1
2
3
–
5
6
Data Register
DIO2 = P2 (SFR 0xA0)
--
DIO3 = P3 (SFR 0xB0)
--
1
3
4
5
--
Direction Register
0 = input, 1 = output
--
--
--
--
--
--
DIO_DIR2 (SFR 0xA1)
DIO
40
41 42
43
63
40
44
64
31
45
65
38
--
--
--
47
48
68
23
49
69
24
50
51
71
50
LCD Segment
Pin number
60 61 62
95 97 98
67
22
3
70
25
6
Configuration (DIO or
LCD segment)
4
5
6
7
0
1
--
4
5
7
LCD_BITMAP[63:56]
LCD_BITMAP[71:64]
--
Data Register
Direction Register
0 = input, 1 = output
--
44
© 2005-2009 TERIDIAN Semiconductor Corporation
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