FDS 6531/6532 005
Data Sheet 71M6531D/F-71M6532D/F
should be enabled by MPU code that is executed during the pre-boot interval (60 CKMPU cycles before
the primary boot sequence begins). Once security is enabled, the only way to disable it is to perform a
global erase of the flash, followed by a chip reset.
The first 60 cycles of the MPU boot code are called the pre-boot phase because during this phase the
ICE is inhibited. A read-only status bit, PREBOOT, identifies these cycles to the MPU. Upon completion
of pre-boot, the ICE can be enabled and is permitted to take control of the MPU.
The security enable bit, SECURE, is reset whenever the chip is reset. Hardware associated with the bit
permits only ones to be written to it. Thus, pre-boot code may set SECURE to enable the security feature
but may not reset it. Once SECURE is set, the pre-boot code is protected and no external read of program
code is possible
Specifically, when SECURE is set, the following applies:
•
•
The ICE is limited to bulk flash erase only.
Page zero of flash memory, the preferred location for the user’s pre-boot code, may not be
page-erased by either MPU or ICE. Page zero may only be erased with global flash erase.
•
Write operations to page zero, whether by MPU or ICE are inhibited.
MPU/CE RAM:
The 71M6531D/F and 71M6532D/F include 4 KB of static RAM memory on-chip (XRAM) plus 256-bytes
of internal RAM in the MPU core. The 4 KB of static RAM are used for data storage for MPU and CE op-
erations.
1.5.6 Optical Interface
The device includes an interface to implement an IR/optical port. The pin OPT_TX is designed to directly
drive an external LED for transmitting data on an optical link. The pin OPT_RX has the same threshold
as the RX pin, but can also be used to sense the input from an external photo detector used as the re-
ceiver for the optical link. OPT_TX and OPT_RX are connected to a dedicated UART port (UART1).
The OPT_TX and OPT_RX pins can be inverted with configuration bits OPT_TXINV and OPT_RXINV, re-
spectively. Additionally, the OPT_TX output may be modulated at 38 kHz. Modulation is available when
system power is present (i.e. not in BROWNOUT mode). The OPT_TXMOD bit enables modulation. Duty
cycle is controlled by OPT_FDC[1:0], which can select 50%, 25%, 12.5% and 6.25% duty cycle. 6.25% duty
cycle means OPT_TX is low for 6.25% of the period. Figure 9 illustrates the OPT_TX generator.
When not needed for the optical UART, the OPT_TX pin can alternatively be configured as DIO2,
WPULSE, or VARPULSE. The configuration bits are OPT_TXE[1:0]. Likewise, OPT_RX can alternately
be configured as DIO1. Its control is OPT_RXDIS.
V3P3
VARPULSE
WPULSE
DIO2
Internal
3
2
1
OPT_TX
from
OPT_TX UART
A
MOD
B
0
OPT_TXINV
EN DUTY
2
OPT_TXE[1:0]
OPT_TXMOD
OPT_FDC
OPT_TXMOD = 1,
OPT_FDC = 2 (25%)
OPT_TXMOD = 0
A
B
A
B
1/38kHz
Figure 9: Optical Interface
v1.2
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