W159B
Absolute Maximum Ratings [11]
Stresses greater than those listed in this table may cause
permanent damage to the device. These represent a stress
rating only. Operation of the device at these or any other condi-
tions above those specified in the operating sections of this
specification is not implied. Maximum conditions for extended
periods may affect reliability.
.
Parameter
VDD, VIN
TSTG
TA
Description
Voltage on any pin with respect to GND
Storage Temperature
Rating
–0.± to +7.0
–6± to +1±0
0 to +70
Unit
V
°C
°C
°C
kV
Operating Temperature
TB
Ambient Temperature under Bias
Input ESD Protection
–±± to +12±
2 (min.)
ESDPROT
DC Electrical Characteristics: TA = 0°C to +70°C, VDDQ3 = 3.3V±±%, VDDQ2 = 2.±V±±%
Parameter
Description
Test Condition
Min.
Typ.
Max.
Unit
Supply Current
IDD-3.3V
IDD-2.±
Combined 3.3V Supply Current
Combined 2.±V Supply Current
CPU0:3 =133 MHz[11]
CPU0:3 =133 MHz[11]
160
90
mA
mA
Logic Inputs (All referenced to VDDQ3 = 3.3V)
VIL
Input Low Voltage
GND –
0.3
0.8
V
V
VIH
Input High Voltage
2.0
VDD
0.3
+
IIL
IIH
IIL
IIH
Input Low Current[13]
–2±
10
–±
±
µA
µA
µA
µA
Input High Current[13]
Input Low Current, SEL133/100#[13]
Input High Current, SEL133/100#[13]
Clock Outputs
CPU, CPUdiv2, IOAPIC (Referenced to VDDQ2
)
Test Condition
IOL = 1 mA
Min.
Typ.
Max.
Unit
mV
V
VOL
VOH
IOL
Output Low Voltage
Output High Voltage
Output Low Current
Output High Current
±0
IOH = –1 mA
VOL = 1.2±V
VOH = 1.2±V
Test Condition
IOL = 1 mA
2.2
4±
6±
6±
100
100
Max.
±0
mA
mA
Unit
mV
V
IOH
4±
48MHz, REF (Referenced to VDDQ3
)
Min.
Typ.
VOL
VOH
IOL
Output Low Voltage
Output High Voltage
Output Low Current
Output High Current
IOH = –1 mA
VOL = 1.±V
3.1
4±
6±
6±
100
100
Max.
±0
mA
mA
Unit
mV
V
IOH
VOH = 1.±V
4±
3V33, 3V66 (Referenced to VDDQ3
)
Test Condition
IOL = 1 mA
Min.
Typ.
VOL
VOH
IOL
Output Low Voltage
Output High Voltage
Output Low Current
Output High Current
IOH = –1 mA
VOL = 1.±V
3.1
70
6±
100
9±
14±
13±
mA
mA
IOH
VOH = 1.±V
Notes:
11. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
12. All clock outputs loaded with 6" 60 transmission lines with 20-pF capacitors.
13. W1±9B logic inputs have internal pull-up devices, except SEL133/100# (pull-ups not CMOS level).
:
Rev 1.0,November 21, 2006
Page ± of 10
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