W159B
3V33 Clock Outputs, 3V33_0:1 (Lump Capacitance Test Load = 30 pF)
Parameter
Description
Period
Test Condition/Comments
Measured on rising edge at 1.±V[19]
Min. Typ. Max. Unit
tP
tH
tL
30
12
12
1
ns
ns
High Time
Low Time
Duration of clock cycle above 2.4V
Duration of clock cycle below 0.4V
ns
tR
tF
Output Rise Edge Rate Measured from 0.4V to 2.4V
4
4
V/ns
V/ns
%
Output Fall Edge Rate
Duty Cycle
Measured from 2.4V to 0.4V
1
tD
tJC
Measured on rising and falling edge at 1.±V
4±
±±
±00
Jitter, Cycle-to-Cycle
Measured on rising edge at 1.±V. Maximum difference of
cycle time between two adjacent cycles.
ps
tSK
tO
Output Skew
Measured on rising edge at 1.±V
±00
3.0
ps
ns
3V66 to 3V33 Clock
Skew
Covers all 3V66 outputs. Measured on rising edge at 1.±V.
3V66 leads 3V33 output.
1.±
1.±
tq
CPU to 3V33 Clock
Skew
Covers all 3V33 outputs. Measured on rising edge at 1.±V.
CPU leads 3V33 output.
4.0
3
ns
fST
Frequency Stabilization Assumes full supply voltage reached within 1 ms from
power-up. Short cycles exist prior to frequency stabilization.
ms
from Power-up (cold
start)
Zo
AC Output Impedance
Average value during switching transition. Used for deter-
mining series termination value.
1±
:
REF Clock Outputs, REF0:1 (Lump Capacitance Test Load = 20 pF)
Parameter
Description
Frequency, Actual
Output Rise Edge Rate
Output Fall Edge Rate
Duty Cycle
Test Condition/Comments
Frequency generated by crystal oscillator
Measured from 0.4V to 2.4V
Min.
Typ.
14.318
Max. Unit
f
MHz
tR
0.±
0.±
4±
2
2
V/ns
V/ns
%
tF
Measured from 2.4V to 0.4V
tD
Measured on rising and falling edge at 1.±V
±±
3
fST
FrequencyStabilizationfrom Assumes full supply voltage reached within
1 ms from power-up. Short cycles exist prior to
frequency stabilization.
ms
Power-up (cold start)
Zo
AC Output Impedance
Average value during switching transition. Used
for determining series termination value.
2±
:
Note:
19. 3V33 clock is CPU/4 for CPU = 133 MHz and CPU/3 for CPU = 100 MHz.
Rev 1.0,November 21, 2006
Page 7 of 10
SPECTRALINEAR [ SPECTRALINEAR INC ]
