W159B
Spread Spectrum System FTG for SMP Systems
Features
• Maximized EMI suppression using Cypress’s spread
spectrum technology (0.5% down spread)
• Seven skew-controlled copies of CPU and 16.667-MHz
synchronous APIC output
• Two copies of fixed-frequency 33 MHz outputs
• Four copies of 66 MHz fixed-frequency outputs
• Two copies of CPU/2 outputs for synchronous memory
reference
• One copy of 48 MHz USB output
• Two copies of 14.31818 MHz reference clock
• Programmable to 133 or 100 MHz operation
• Power management control pins for clock stop and
shut down
• Available in 56-pin SSOP
Key Specifications
Supply Voltages: ......... V
DDQ3
= 3.3V±5%V
DDQ2
= 2.5V±5%
CPU Output Jitter: ...................................................... 200 ps
CPUdiv2, 3V33, APIC Output Jitter: ........................... 250 ps
CPU, 3V33 Output Edge Rate: .................................. >1 V/ns
48-MHz, 3V66, REF Output Jitter: .............................. 500 ps
CPU0:6, CPUdiv2_0:1 Output Skew: ......................... 175 ps
3V66, APIC0:6, 3V33 Output Skew: ........................... 250 ps
CPU to 3V66 Output Offset:.......... 0.0 to 1.5 ns (3V66 leads)
3V66 to 3V33 Output Offset:......... 1.5 to 3.0 ns (3V66 leads)
CPU to APIC Output Offset:.............1 to 3.0 ns (CPU Leads)
CPU to 3V33 Output Offsets:........1.0 to 4.0 ns (CPU Leads)
Logic inputs, except SEL133/100#, have 100-k
resistors.
Table 1. Pin Selectable Frequency
SEL133/100#
1
0
CPU0:6 (MHz)
133 MHz
[1]
100
pull-up
PCI
33.3 MHz
33.3 MHz
MHz
Block Diagram
X1
X2
Pin Configuration
2
REF_[0:1]
5
CPU_[0:4]
XTAL
OSC
6W/4W#
2
CPU_[5:6]
2
SPREAD#
÷2
CPUdiv2_[0:1]
PLL 1
4
SEL133/100#
÷2/÷1.5
3V66_[0:3]
2
PWRDWN#
÷2
3V33_[0:1]
Power
Down
Logic
FIXAPIC#
5
÷4
2
APIC_[5:6]
APIC_[0:4]
APIC2
GND
APIC1
APIC0
VDDQ2
X1
X2
VDDQ3
REF0/FIXAPIC#*
REF1/TEST#*
GND
VDDQ3
GND
48MHz
VDDQ3
3V66_0
3V66_1
VDDQ3
GND
3V66_2
3V66_3
VDDQ3
3V33_0
3V33_1
GND
6W/4W#*
VDDQ3
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
APIC3
APIC4
VDDQ2
APIC5
APIC6
GND
SPREAD#*
VDDQ2
CPU0
CPU1
GND
GND
CPU2
CPU3
VDDQ2
VDDQ2
CPU4
CPU5
GND
GND
CPU6
VDDQ2
PWRDWN#*
GND
CPUdiv2_0
CPUdiv2_1
VDDQ2
SEL133/100#
PLL2
1
Note:
1. Pins denoted by * have a 250-k pull-up resistor. Design
should not rely solely on internal pull-up resistor to set I/O pins
HIGH.
48MHz
W159B
Rev 1.0, November 21, 2006
2200 Laurelwood Road, Santa Clara, CA 95054
Tel:(408) 855-0555
Fax:(408) 855-0550
Page 1 of 10
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