W159B
Pin Definitions
Pin
No.
Pin
Type
Pin Name
Pin Description
CPU0:6
48,47,44,43,
40, 39, 36
O
CPU Clock Outputs 0 through 6: These seven CPU clocks run at a frequency set
by SEL133/100#. Output voltage swing is set by the voltage applied to VDDQ2. For
4-way SMP systems that do not require more than ± CPU outputs, CPU± and CPU6
can be disabled by asserting 6W/4W# during power-up.
CPUdiv2_ 0:1
3V33_0:1
32, 31
O
Synchronous Memory Reference Clock Output 0 through 1: Reference clock
for Direct RDRAM clock generators running at 1/2 CPU clock frequency. Output
voltage swing is set by the voltage applied to VDDQ2. For systems using SDRAM,
CPUdiv2_0:1 output can be disabled by tying VDDQ2 on pin 30 to GND.
23, 24
9
O
33 MHz Fixed-Frequency Output: These are fixed-frequency outputs that can be
used to drive PCI devices.
REF0/
FIXAPIC#*
I/O
14.318 MHz Reference Clock Output/APIC Speed Select: During normal opera-
tions, this is a 3.3V 14.318-MHz reference output. During power-up, it is sampled
to determine the operating frequency of APIC. If the sample is a “1,” APIC will be
set at CPU/4. If it is a “0,” APIC will be fixed at 16.667 MHz.
REF1/TEST#*
APIC0:6
10
I/O
O
14.318 MHz Reference Clock Output/Test Mode: During normal operations, this
is a 3.3V 14.318-MHz reference output. The input is sampled at power-up to
determine if the device should initialize for normal operations or test mode.
4, 3, 1, ±6, ±±
±3, ±2
Synchronous I/OAPIC Clock Outputs: APIC output frequency is determined by
FIXAPIC# strapping. For 4-way SMP systems that do not require more than ± APIC
outputs, APIC± and APIC6 can be disabled by asserting 4W/6W# during power up.
48MHz
14
O
48 MHz Output: Fixed 48-MHz USB output. Output voltage swing is controlled by
voltage applied to VDDQ3.
3V66_0:3
16, 17, 20, 21
29
O
I
66 MHz Output 0 through 3: Fixed 66-MHz outputs.
SEL133/100#
Frequency Selection Input: 3.3V LVTTL-compatible input that selects CPU output
frequency as shown in Table 1.
X1
6
7
I
O
I
Crystal Connection or External Reference Frequency Input: Connect to either
a 14.318-MHz crystal or other reference signal.
X2
Crystal Connection: An output connection for an external 14.318-MHz crystal. If
using an external reference, this pin must be left unconnected.
6W/4W#*
26
4-way/6-way Output Select: This input can be changed after initialization and has
an internal pull-up resistor. If left unconnected during power-up, the outputs are
configured so that all CPU and APIC outputs are active. If it is pulled down during
power-up, CPU±:6 and APIC±:6 will be disabled.
SPREAD#
PWRDWN#
GND
±0
34
I
I
Active LOW Spread Spectrum Enable: 3.3V LVTTL-compatible input that enables
spread spectrum mode when held LOW.
Active LOW Power Down Input: 3.3V LVTTL-compatible asynchronous input that
requests the device to enter power down mode.
2, 11, 13, 19,
2±,28,33,37,
38, 4±, 46, ±1
G
Ground Connection
VDDQ3
VDDQ2
8, 12, 1±, 18,
22, 27
P
P
Power Connection:Power supply for 3V33, 3V66, 48MHz, and REF output buffers,
core circuitry and PLL circuitry. Connect to 3.3V supply.
±, 30, 3±, 41,
42, 49, ±4
Power Connection: Power supply for APIC and CPU, CPUdiv2 output buffers.
Connect to 2.±V supply.
provides skew-controlled PCI and IOAPIC clocks
synchronous to CPU clock, 48-MHz Universal Serial Bus
Overview
The W1±9B is designed to provide the essential frequency
sources to work with advanced multiprocessing Intel® archi-
tecture platforms. Split voltage supply signaling provides 2.±V
and 3.3V clock frequencies operating up to 133 MHz.
(USB) clock, and replicates the 14.31818-MHz reference
clock.
All CPU, PCI, and IOAPIC clocks can be synchronously
modulated for spread spectrum operations. Cypress employs
proprietary techniques that provide the maximum EMI
reduction while minimizing the clock skews that could reduce
From a low-cost 14.31818-MHz reference crystal oscillator,
the W1±9B generates 2.±V clock outputs to support CPUs,
core logic chip set, and Direct RDRAM clock generators. It also
Rev 1.0,November 21, 2006
Page 2 of 10
SPECTRALINEAR [ SPECTRALINEAR INC ]
