W159B
CPUdiv2 Clock Outputs, CPUdiv2_0:1 (Lump Capacitance Test Load = 20 pF)
CPU = 133 MHz
Min. Typ. Max. Min. Typ. Max. Unit
CPU = 100 MHz
Parameter
Description
Period
Test Condition/Comments
Measured on rising edge at 1.2±V
Duration of clock cycle above 2.0V
Duration of clock cycle below 0.4V
tP
tH
tL
1±
±.2±
±.0±
1
1±.3
20
7.±
7.3
1
20.4
ns
ns
High Time
Low Time
ns
tR
tF
tD
Output Rise Edge Rate Measured from 0.4V to 2.0V
Output Fall Edge Rate Measured from 2.0V to 0.4V
4
4
4
4
V/ns
V/ns
%
1
1
Duty Cycle
Measured on rising and falling edge at
1.2±V
4±
±±
4±
±±
tJC
Jitter, Cycle-to-Cycle
Measured on rising edge at 1.2±V.
Maximum difference of cycle time
between two adjacent cycles.
2±0
2±0
ps
tSK
fST
Output Skew
Measured on rising edge at 1.2±V
17±
3
17±
3
ps
Frequency Stabili-
zation from Power-up
(cold start)
Assumes full supply voltage reached
within 1ms frompower-up. Shortcycles
exist prior to frequency stabilization.
ms
Zo
AC Output Impedance Average value during switching
transition. Used for determining series
termination value.
20
20
:
APIC Clock Outputs, APIC0:2 (Lump Capacitance Test Load = 20 pF)
Parameter
Description
Frequency
Test Condition/Comments
Min
Typ
16.67
Max
Unit
f
Note 21
MHz
V/ns
V/ns
%
tR
tF
tD
fST
Output Rise Edge Rate
Output Fall Edge Rate
Duty Cycle
Measured from 0.4V to 2.0V
Measured from 2.0V to 0.4V
1
1
4
4
Measured on rising and falling edge at 1.2±V
Assumes full supply voltage reached within
4±
±±
3
Frequency Stabilization
ms
from Power-up (cold start) 1 ms from power-up. Short cycles exist prior to
frequency stabilization.
Zo
AC Output Impedance
Averagevalueduringswitchingtransition.Used
for determining series termination value.
20
:
Note:
21. APIC clock is CPU/8 for CPU = 133 MHz and CPU/6 for CPU = 100 MHz.
Rev 1.0,November 21, 2006
Page 9 of 10
SPECTRALINEAR [ SPECTRALINEAR INC ]
