FEDL87V2107-01
OKI Semiconductor
ML87V2107
2.2.7 Detection of Delay between Input and Output
This IC can read the delay IOPD[9:0]( SUB:46h-bit[7:0], SUB:47h-bit[1:0]) between input and output in line
units.
The IC can also read the standard signal checking STD(SUB:47h-bit[6]) by checking the interleaving of input
Sync. signals.
By using these signals, a voice delay adjustment for the image delay is enabled in the external voice delay.
When this method is used, ICLK and OCLK must be synchronized and the input Sync. signal must satisfy
interleaving.
*In this condition, the input/output delay is maintained at a constant level and no phase change occurs.
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