FEDL674000-02
OKI Semiconductor
ML674000
DESCRIPTION OF FUNCTIONS
CPU
CPU core:
ARM7TDMI
Operating frequency:
Instructions:
1 MHz to 33 MHz
ARM instruction (32-bit length) and Thumb instruction (16-bit length) can be mixed.
General register bank:
Built-in barrel shifter:
Multiplier:
31 × 32 bits
ALU and barrel shift operations can be executed by one instruction.
32 bits × 8 bits (Modified Booth’s Algorithm)
Built-in debug function: JTAG interface, break point register
Built-in Memory
RAM:
8 KB (2K × 32 bits)
Connected to processor bus (read: 1 cycle access, write: 2 cycle access)
Interrupt Controller
Fast interrupt input (FIQ) and interrupt input (IRQ) are employed as interrupt input signals of ARM core. The
interrupt controller controls these interrupt signals going to ARM core.
(1) Interrupt sources of ML674000
FIQ: 1 source, external source (external pin: EFIQ_N)
IRQ: 23 sources, internal sources : 19, external sources : 4 (external pins: EXINT[3:0])
(2) Interrupt priority level
Priority can be set in 8 levels for each source.
(3) External interrupt pin input
Level sense: Interrupt signal level is selected.
Edge sense: Rise or fall is selected.
(4) External fast interrupt pin input
Edge sense: Fall edge is detected.
Timer
7 channels of 16-bit reload timers are employed. Of these, 1 channel is used as system timer for OS.
The timers of other 6 channels are used in application software.
(1) System timer: 1 channel
16-bit auto reload timer: Used as system timer for OS
(This timer is incorporated in µPLAT-7B.)
Interval mode
(2) Application timer: 6 channels
16-bit auto reload timer
One shot, interval mode
Clock can be set for each channel
WDT
This MCU contains a Watch Dog Timer that can also function as an interval timer.
(1) 16-bit timer
(2) Watch dog timer or interval timer mode can be selected
(3) Interrupt or reset generation
- Watchdog timer mode: generates reset or interrupt when the timer is overflows.
- Interval timer mode: generates interrupt when the timer reaches an overflow condition.
(4) Maximum period: 200 msec or longer
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