FEDL674000-02
OKI Semiconductor
ML674000
PWM
This MCU contains two PWM (Pulse Width Modulation) channels which can change duty cycle within a certain
fixed period. The PWM output resolution is 16 bits for each channel.
Serial Interface
This LSI contains two channels of serial interface.
(1) UART without FIFO: 1 channel
This serial interface is incorporated in µPLAT-7B.
(2) UART with 16-byte FIFO: 1 channel
This is ACE (Asynchronous Communication Element) equivalent in function to 16550A. It has 16-byte FIFO
in both sending and receiving.
GPIO
This LSI contains two 16-bit parallel ports.
(1) Input or output can be selected for each bit.
(2) Interrupt can be used for all 16 bits of each channel, and all GPIO pins can be used as interrupt inputs.
(3) Interrupt mask and interrupt mode (level) can be set for all bits.
(4) Configured as inputs immediately after reset.
AD Converter
This is a successive approximation type AD converter.
(1) 10 bits × 8 channels
(2) Sample and hold function
(3) Scan mode and select mode are supported
(4) Interrupt is generated after completion of conversion.
(5) Minimum conversion time of 5 µs.
DMAC
This MCU contains a two channel direct memory access controller which transfers data between memory and
memory, between I/O and memory and between I/O and I/O.
(1) Number of channels: 2 channels
(2) Channel priority level: Fixed mode
Channel priority level is always fixed (channel 0 > 1).
Roundrobin
Priority level of the channel requested for transfer is kept lowest.
(3) Maximum number of transfers: 65,536 times (64K times)
(4) Data transfer size: Byte (8 bits), half-word (16 bits), word (32 bits)
(5) Bus request system:
Cycle steal mode
Bus request signal is asserted for each DMA transfer cycle.
Burst mode
Bus request signal is asserted until all transfers of transfer cycles are complete.
(6) DMA transfer request: Software request
By setting the software transfer request bit inside DMAC, the CPU starts DMA
transfer.
External request
DMA transfer is started by external request allocated to each channel.
(7) Interrupt request: Interrupt request is generated in CPU after the end of DMA transfers for the set number
of transfer cycles or after occurrence of error.
Interrupt request signal is output separately for each channel.
Interrupt request signal output can be masked for each channel.
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