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EM785830AAP 参数 Datasheet PDF下载

EM785830AAP图片预览
型号: EM785830AAP
PDF下载: 下载PDF文件 查看货源
内容描述: 8位微控制器 [8-BIT MICRO-CONTROLLER]
分类和应用: 微控制器
文件页数/大小: 43 页 / 394 K
品牌: ELAN [ ELAN MICROELECTRONICS CORP ]
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EM785830AA  
8-bit Micro-controller  
Bit 6 (PWM1E): PWM1 enable bit  
0 Î PWM1 is off (default value), and its related pin carries out the PC1 function;  
1 Î PWM1 is on, and its related pin will be set to output automatically.  
Bit 7 (PWM2E): PWM2 enable bit  
0 Î PWM2 is off (default value), and its related pin carries out the PC2 function.  
1 Î PWM2 is on, and its related pin will be set to output automatically.  
R6 (PORT6 I/O data, SPI data buffer)  
PAGE0 (PORT6 I/O data register)  
7
6
5
4
3
2
1
0
P67  
R/W  
P66  
R/W  
P65  
R/W  
P64  
R/W  
P63  
R/W  
P62  
R/W  
X
-
X
-
Bit0 ~Bit1: Unused register. These two bits are not allowed to use.  
Bit2 ~ Bit7 (P62 ~ P67) : 6-bit PORT6(2~7) I/O data register  
User can use IOC register to define input or output each bit.  
PAGE1 : (undefined) not allowed to use  
PAGE2 (SPI data buffer)  
7
6
5
4
3
2
1
0
SPIB7  
R/W  
SPIB6  
R/W  
SPIB5  
R/W  
SPIB4  
R/W  
SPIB3  
R/W  
SPIB2  
R/W  
SPIB1  
R/W  
SPIB0  
R/W  
Bit 0 ~ Bit 7 (SPIB0 ~ SPIB7) : SPI data buffer  
If you write data to this register, the data will write to SPIW register. If you read this data, it will read the  
data from SPIR register. Please refer to figure7  
PAGE3 (DT1L: the Least Significant Byte ( Bit 7 ~ Bit 0) of Duty Cycle of PWM1)  
7
6
5
4
3
2
1
0
PWM1[7] PWM1[6] PWM1[5] PWM1[4] PWM1[3] PWM1[2] PWM1[1] PWM1[0]  
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0  
A specified value keeps the output of PWM1 to stay at high until the value matches with TMR1.  
R7 (PORT7 I/O data, Data RAM bank)  
PAGE0 (PORT7 I/O data register)  
7
6
5
4
3
2
1
0
X
-
P76  
R/W  
P75  
R/W  
P74  
R/W  
P73  
R/W  
X
-
X
-
P70  
R/W  
Bit 0 ; Bit3 ~ Bit 7 (P73 ~ P76) : 5-bit PORT7 I/O data register  
User can use IOC register to define input or output each bit.  
Bit1~2, Bit 7: Unused register. These three bits are not allowed to use.  
PAGE1 (Data RAM bank selection bits)  
7
-
6
-
5
AD9  
R
4
AD8  
R
3
2
1
0
0
ADRES  
R/W-0  
RAM_B0  
R/W-0  
-
R/W-0  
Bit 0(RAM_B0) : Data RAM bank selection bits  
Each bank has address 0 ~ address 255 which is total 256 (0.25k) bytes RAM size.  
Data RAM bank selection : (Total RAM = 0.5K)  
RAM_B0 RAM bank  
0
1
Bank0  
Bank1  
Bit 1 : (undefined) not allowed to use. This bit must clear to 0.  
__________________________________________________________________________________________________________________________________________________________________  
* This specification is subject to be changed without notice.  
13  
12/1/2004 V1.6  
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