EM785830AA
8-bit Micro-controller
The address for data RAM is accessed from R8 PAGE1. The data RAM bank is selected by R7 PAGE1 Bit0
(RAM_B0).
PAGE2 : (undefined) not allowed to use
PAGE3 (DT2L: the Least Significant Byte ( Bit 7 ~ Bit 0 ) of Duty Cycle of PWM2)
7
6
5
4
3
2
1
0
PWM2[7] PWM2[6] PWM2[5] PWM2[4] PWM2[3] PWM2[2] PWM2[1] PWM2[0]
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
A specified value keeps the output of PWM2 to stay at high until the value matches with TMR2.
RA (PLL, Main clock selection, Watchdog timer)
PAGE0 (PLL enable bit, Main clock selection bits, Watchdog timer enable bit)
7
0
6
5
4
3
2
X
-
1
X
-
0
PLLEN
R/W-0
CLK2
R/W
CLK1
R/W
CLK0
R/W
WDTEN
R/W-0
R/W-0
Bit 0(WDTEN) : Watch dog control bit
User can use WDTC instruction to clear watch dog counter. The counter 's clock source is 32768/2 Hz. If
the prescaler assigns to TCC. Watch dog will time out by (1/32768 )*2 * 256 = 15.616mS. If the
prescaler assigns to WDT, the time of time out will be more times depending on the ratio of prescaler.
0/1 Î disable/enable
Bit 1~Bit 2 : Unused, these 2 bits are not allowed to use.
Bit 3 ~ Bit 5 (CLK0 ~ CLK2) : MAIN clock selection bits
User can choose different frequency of main clock by CLK1 and CLK2. All the clock selection is list below.
PLLEN
CLK2
CLK1
CLK0
Sub clock
MAIN clock CPU clock
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
32.768kHz 447.829kHz 447.829kHz (Normal mode)
32.768kHz 895.658kHz 895.658kHz (Normal mode)
32.768kHz 1.791MHz
32.768kHz 3.582MHz
32.768kHz 7.165MHz
1.791MHz (Normal mode)
3.582MHz (Normal mode)
7.165MHz (Normal mode)
32.768kHz 10.747MHz 10.747MHz (Normal mode)
32.768kHz 14.331MHz 14.331MHz (Normal mode)
Can’t allowed to use
don’t care don’t care don’t care 32.768kHz don’t care
32.768kHz (Green mode)
Bit 6(PLLEN) : PLL's power control bit which is CPU mode control register
0/1 Î disable PLL/enable PLL
If enable PLL, CPU will operate at normal mode (high frequency). Otherwise, it will run at green mode
(low frequency, 32768 Hz).
447.8293kHz ~14.3MHz
CLK2 ~ CLK0
PLL circuit
1
System
clock
switch
0
ENPLL
Sub-clock
32.768kHz
Fig.7 The relation between 32.768kHz and PLL
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
15
12/1/2004 V1.6
ELAN [ ELAN MICROELECTRONICS CORP ]
