THEORY OF OPERATION
+5V
ADC7802 uses the advantages of advanced CMOS technol-
ogy (logic density, stable capacitors, precision analog
switches, and low power consumption) to provide a precise
12-bit analog-to-digital converter with on-chip sampling and
four-channel analog-input multiplexer.
1
2
3
4
5
6
7
8
9
SFR
AIN0
AIN1
AIN2
AIN3
28
NC
V
A
+
10nF
NC
10µF
AGND 27
CAL 26
A1 25
0-5V
Input
100kΩ
The input stage consists of an analog multiplexer with an
address latch to select from four input channels.
A0 24
+5V
VREF+
CLK 23
BUSY 22
HBE 21
WR 20
CS 19
RD 18
D0 17
+
The converter stage consists of an advanced successive
approximation architecture using charge redistribution on a
capacitor network to digitize the input signal. A temperature-
stabilized differential auto-zeroing circuit is used to mini-
mize offset errors in the comparator. This allows offset errors
to be corrected during the acquisition phase of each conver-
sion cycle.
10nF
10µF
BUSY
VREF
DGND
VD
–
High Byte
Enable Command
Convert Command
10 D7
11 D6
12 D5
13 D4
14 D3
BUSY
LOW
LOW
LOW
Data Bit 7
Data Bit 6
Data Bit 5
Data Bit 4
Data Bit 3
Read Command
Data Bit 0
(LSB)
Linearity errors in the binary weighted main capacitor net-
work are corrected using a capacitor trim network and
correction factors stored in on-chip memory. The correction
terms are calculated by a microcontroller during a calibration
cycle, initiated either by power-up or by applying an external
calibration signal at any time. During conversion, the correct
trim capacitors are switched into the main capacitor array as
needed to correct the conversion accuracy. This is faster than
a complex digital error correction system, which could slow
down the throughput rate. With all of the capacitors in both
the main array and the trim array on the same chip, excellent
stability is achieved, both over temperature and over time.
Data Bit 8
D1 16
Data Bit 1 Data Bit 9
Data Bit 11
(MSB)
D2 15
Data Bit 2 Data Bit 10
HBE Input HBE Input
HBE Input
LOW
HBE Input
HIGH
LOW
HIGH
FIGURE 1. Basic Operation.
Figures 2 and 3 show the full conversion sequence and the
timing to initiate a conversion.
For flexibility, timing circuits include both an internal clock
generator and an input for an external clock to synchronize
with external systems. Standard control signals and three-
state input/output registers simplify interfacing ADC7802 to
most micro-controllers, microprocessors or digital storage
systems.
CALIBRATION
A calibration cycle is initiated automatically upon power-up
(or after a power failure). Calibration can also be initiated by
the user at any time by the rising edge of a minimum 100ns-
wide LOW pulse on the CAL pin (pin 26), or by setting D1
HIGH in the Special Function Register (see SFR section). A
calibration command will initiate a calibration cycle, regard-
less of whether a conversion is in process. During a calibra-
tion cycle, convert commands are ignored.
Finally, this performance is matched with the low-power
advantages of CMOS structures to allow a typical power
consumption of 10mW.
Calibration takes 168 clock cycles, and a normal conversion
(17 clock cycles) is added automatically. For maximum
accuracy, the supplies and reference need to be stable during
the calibration procedure. To ensure that supply voltages and
reference voltages have settled and are stable, an internal
timer provides a waiting period of 42,425 clock cycles
between power-up/power-failure and the start of the calibra-
tion cycle.
OPERATION
BASIC OPERATION
Figure 1 shows the simple circuit required to operate
ADC7802 in the Transparent Mode, converting a single
input channel. A convert command on pin 20 (WR) starts a
conversion. Pin 22 (BUSY) will output a LOW during the
conversion process (including sample acquisition and con-
version), and rises only after the conversion is completed.
The two bytes of output data can then be read using pin 18
(RD) and pin 21 (HBE).
READING DATA
Data from the ADC7802 is read in two 8-bit bytes, with the
Low byte containing the 8 LSBs of data, and the High byte
containing the 4 MSBs of data. The outputs are coded in
straight binary (with 0V = 000 hex, 5V = FFF hex), and the
data is presented in a right-justified format (with the LSB as
the most right bit in the 16-bit word). Two read operations are
required to transfer the High byte and Low byte, and the
bytes are presented according to the input level on the High
Byte Enable pin (HBE).
STARTING A CONVERSION
A conversion is initiated on the rising edge of the WR input,
with valid signals on A0, A1 and CS. The selected input
channel is sampled for five clock cycles, during which the
comparator offset is also auto-zeroed to below 1/4LSB of
error. The successive approximation conversion takes place
during clock cycles 6 through 17.
®
ADC7802
6
BB [ BURR-BROWN CORPORATION ]
