TRANSPARENT MODE
In this mode, the data from a conversion is latched into the
output buffers only after a conversion is complete, and
remains there until the next conversion is completed. The
conversion result is valid during the next conversion. This
allows the data to be read even after a new conversion is
started, for faster system throughput.
This is the default mode for ADC7802. In this mode, the
conversion decisions from the successive approximation
register are latched into the output register as they are made.
Thus, the High byte (the 4 MSBs) can be read after the end
of the ninth clock cycle (five clock cycles for the mux
settling, sample acquisition and auto-zeroing of the compara-
tor, followed by the four clock cycles for the 4MSB deci-
sions.) The complete 12-bit data is available after BUSY has
gone HIGH, or the internal status flag goes LOW (D7 when
HBE is HIGH).
TIMING CONSIDERATIONS
Table I and Figures 3 through 8 show the digital timing of
ADC7802 under the various operating modes. All of the
critical parameters are guaranteed over the full –40oC to
+85oC operating range for ease of system design.
LATCHED OUTPUT MODE
SPECIAL FUNCTION REGISTER (SFR)
This mode is activated by writing a HIGH to D0 and LOWs
to D1 to D7 in the Special Function Register with CS and WR
LOW and SFR and HBE HIGH. (See the discussion of the
Special Function Register below.)
An internal register is available, either to determine addi-
tional data concerning the ADC7802, or to write additional
instructions to the converter. Access to the Special Function
Register is made by driving SFR HIGH.
SYMBOL
PARAMETER (1)
MIN
TYP
MAX
UNITS
(2)
t1
t2
CS to WR Setup Time
0
100
0
0
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WR or CAL Pulse Width
(2)
t3
CS to WR Hold Time
0
0
t4
WR to BUSY Propagation Delay
20
0
50
150
t5
A0, A1, HBE, SFR Valid to WR Setup Time
A0, A1, HBE, SFR Valid to WR Hold Time
BUSY to CS Setup Time
t6
20
0
t7
(2)
t8
CS to RD Setup Time
0
0
0
0
0
t9
RD Pulse Width
100
0
t10
t11
t12
t13
t14
t15
t16
t17
CS to RD Hold Time (2)
HBE, SFR to RD Setup Time
HBE, SFR to RD Hold Time
50
0
(3)
RD to Valid Data (Bus Access Time)
80
90
150
180
60
(3)
RD to Hi-Z Delay (Bus Release Time)
(3)
RD to Hi-Z Delay For SFR
20
100
20
Data Valid to WR Setup Time
Data Valid to WR Hold Time
NOTES: (1) All input control signals are specified with tRISE = tFALL = 20ns (10% to 90% of 5V) and timed from a voltage level of 1.6V. Data is timed from VIH
,
VIL, VOH or VOL. (2) The internal RD pulse is performed by a NOR wiring of CS and RD. The internal WR pulse is performed by a NOR wiring of CS and WR.
(3) Figures 7 and 8 show the measurement circuits and pulse diagrams for testing transitions to and from Hi-Z states.
TABLE I. Timing Specifications (CLK = 1MHz external, TA = –40°C to +85°C).
CS
CS
t2
t3
t1
t8
t10
t12
t12
WR
RD
t5
t6
t11
HBE
SFR
t11
SFR
HBE
VIH
VIL
t14
t13
Valid Data
t16
D0 - D7
SFR Data
D0–D7
t17
FIGURE 5. Writing to the SFR.
FIGURE 6. Reading the SFR.
®
ADC7802
8
BB [ BURR-BROWN CORPORATION ]
