The bytes can be read in either order, depending on the status
of the HBE input. If HBE changes while CS and RD are
LOW, the output data will change to correspond to the HBE
input. Figure 4 shows the timing for reading first the Low
byte and then the High byte.
ADC7802 provides two modes for reading the conversion
results. At power-up, the converter is set in the Transparent
Mode.
1
2
3
4
5
6
7
16
17
18
CLK
WR
Multiplexer Settling,
Offset Auto Zeroing
and Sample Acquisition
Successive
Approximation
Conversion
BUSY
FIGURE 2. Converter Timing.
CS
t1
t2
t3
WR or CAL
t4
BUSY
SFR
t5
t6
VIH
VIL
A0, A1
FIGURE 3. Write Cycle Timing (for initiating conversion or calibration).
BUSY
t7
CS
t8
t9
t10
t8
t10
RD
SFR
t11
t12
t11
t12
HBE
t14
High Byte Data
t13
t13
t14
Low Byte Data
Hi-Z State
Hi-Z
D0 - D7
FIGURE 4. Read Cycle Timing.
®
ADC7802
7
BB [ BURR-BROWN CORPORATION ]
