Table II shows the data in the Special Function Register that
will be transferred to the output bus by driving HBE HIGH
(with SFR HIGH) and initiating a read cycle (driving RD and
CS LOW with WR HIGH as shown in Figure 4.) The Power
Fail flag in the SFR is set when the power supply falls below
about 3V. The flag also means that a new calibration has been
started, and any data written to the SFR has been lost. Thus,
the ADC7802 will again be in the Transparent Mode. Writing
a LOW to D5 in the SFR resets the Power Fail flag. The Cal
Error flag in the SFR is set when an overflow occurs during
calibration, which may happen in very noisy systems. It is
reset by starting a calibration, and remains low after a
calibration without an overflow is completed.
Writing a HIGH to D3 in the FSR puts the ADC7802 in the
Power Down Mode. Power consumption is reduced to 50µW
and D3 remains HIGH. To exit Power Down Mode, either
write a LOW to D3 in the SFR, or initiate a calibration by
sending a LOW to the CAL pin or writing a HIGH to D1.
During Power Down Mode, a pulse on CS and WR will
initiate a single conversion, then the ADC7802 will revert to
power down.
PIN
FUNCTION
DESCRIPTION
Table III shows how instructions can be transferred to the
Special Function Register by driving HBE HIGH (with SFR
HIGH) and initiating a write cycle (driving WR and CS
LOW with RD HIGH.) The timing is shown in Figure 3. Note
that writing to the SFR also initiates a new conversion.
D0
Mode Status
If LOW, Transparent Mode enabled for
data latches. If HIGH, Latched Output
Mode enabled.
D1
CAL Flag
If HIGH, calibration cycle in progress.
D2
D3
D4
Reserved for factory use.
If HIGH, in Power Down Mode.
Reserved for factory use.
Power Down Status
POWER FAIL Flag
CAL ERROR Flag
BUSY Flag
CONTROL LINES
D5
D6
D7
If HIGH, a power supply failure has
occurred. (Supply fell below 3V.)
Table IV shows the functions of the various control lines on
the ADC7802. The use of standard CS, RD and WR control
signals simplifies use with most microprocessors. At the
same time, flexibility is assured by availability of status
information and control functions, both through the SFR and
directly on pins.
If HIGH, an overflow occured during
calibration.
If HIGH, conversion or calibration in
progress.
NOTE: These data are transferred to the bus when a read cycle is initiated
with SFR and HBE HIGH. Reading the SFR with SFR HIGH and HBE LOW
is reserved for factory use at this time, and will yield unpredictable data.
TABLE II. Reading the Special Function Register.
CS/WR
SFR/HBE
D0
D1
D3
D5
D7
D2/D4/D6
Enables Transparent Mode for Data Latches.
Enables Latched Output Mode for Data Latches.
Initiates Calibration Cycle.
Resets Power Fail flag.
Activates Power Down Mode
LOW
LOW
LOW
LOW
LOW
HIGH
HIGH
HIGH
HIGH
HIGH
LOW
HIGH
X
X
X
X
X
HIGH
X
LOW
LOW
LOW
LOW
HIGH
X
X
X
LOW
X
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
X
NOTES: (1) In Power Down Mode, a pulse on CS and WR will initiate a single conversion, then the ADC7802 will revert to power down. (2) X means it can be
either HIGH or LOW without affecting this action. Writing HIGH to D2, D3, D4 or D6, or writing with SFR HIGH and HBE LOW, may result in unpredictable behavior.
These modes are reserved for factory use at this time.
TABLE III. Writing to the Special Function Register.
CS
RD
WR
SFR
HBE
CAL
BUSY
OPERATION
X
X
1
0
0
0
0
0
0
0
X
X
X
1
0
0
1
0
1
0
X
X
X
0↑1
1
1
0
1
0
1
X
X
X
0
0
0
1
1
1
1
X
X
X
X
0
1
1
1
0
0
0↑1
X
1
1
1
1
1
1
1
X
0
X
1
X
X
1
X
X
X
Initiates calibration cycle.
Conversion or calibration in process. Inhibits new conversion from starting.
None. Outputs in Hi-Z State.
Initiates conversion.
Low byte conversion results output on data bus.
High byte conversion results output on data bus.
Write to SFR and rising edge on WR initiates conversion.
Contents of SFR output on data bus.
Reserved for factory use.
Reserved for factory use. (Unpredictable data on data bus.)
1
TABLE IV. Control Line Functions.
®
ADC7802
9
BB [ BURR-BROWN CORPORATION ]
