PIN CONFIGURATIONS
Top View
DIP
Top View
LCC
SFR
AIN0
AIN1
AIN2
AIN3
1
2
3
4
5
6
7
8
9
28 VA
27 AGND
26
4
3
2
1
28 27 26
CAL
25 A1
25 A1
24 A0
24 A0
AIN3
5
6
7
8
9
VREF
+
–
23 CLK
22 BUSY
21 HBE
20 WR
19 CS
VREF
VREF
+
–
23
22 BUSY
21
20 WR
19
CLK
VREF
DGND
VD
DGND
VD
HBE
D7 10
11
D7 10
D6
11
CS
D6
18
RD
D5 12
D4 13
D3 14
17 D0
16 D1
15 D2
12
16
13 14 15
17 18
PIN ASSIGNMENTS
PIN #
NAME
DESCRIPTION
1
SFR
Special Function Register. When connected to a microprocessor address pin, allows access to special functions through D0 to
D7. See the sections discussing the Special Function Register. If not used, connect to DGND. This pin has an internal pull-down.
2 to 5
AIN0 to AIN3 Analog inputs. Channel 0 to channel 3.
6
VREF
VREF
+
Positive voltage reference input. Normally +5V. Must be ≤ VA.
Negative voltage reference input. Normally 0V.
Digital ground. DGND = 0V.
7
–
8
9
DGND
VD
Logic supply voltage. VD = +5V. Must be ≤ V and applied after VA.
A
10 to 17
D0 to D7
Data Bus Input/Output Pins. Normally used to read output data. See section on SFR (Special Function Register) for other
uses.
When SFR is LOW, these function as follows:
10
D7
Data Bit 7 if HBE is LOW; if HBE is HIGH, acts as converter status pin and is HIGH during conversion or calibration, goes
LOW after the conversion is completed. (Acts as an inverted BUSY.)
Data Bit 6 if HBE is LOW; LOW if HBE is HIGH.
Data Bit 5 if HBE is LOW; LOW if HBE is HIGH.
Data Bit 4 if HBE is LOW; LOW if HBE is HIGH.
Data Bit 3 if HBE is LOW; Data Bit 11 (MSB) if HBE is HIGH.
Data Bit 2 if HBE is LOW; Data Bit 10 if HBE is HIGH.
Data Bit 1 if HBE is LOW; Data Bit 9 if HBE is HIGH.
11
12
13
14
15
16
17
D6
D5
D4
D3
D2
D1
D0
Data Bit 0 (LSB) if HBE is LOW; Data Bit 8 if HBE is HIGH.
18
19
20
RD
CS
Read Input. Active LOW; used to read the data outputs in combination with CS and HBE.
Chip Select Input. Active LOW.
WR
Write Input. Active LOW; used to start a new conversion and to select an analog channel via address inputs A0 and A1 in
combination with CS. The minimum WR pulse LOW width is 100ns.
21
22
23
HBE
BUSY
CLK
High Byte Enable. Used to select high or low data output byte in combination with CS and RD, or to select SFR.
BUSY is LOW during conversion or calibration. BUSY goes HIGH after the conversion is completed.
Clock Input. For internal/external clock operation. For external clock operation, connect pin 23 to a 74 HC-compatible clock
source. For internal clock operation, connect pin 23 per the clock operation description.
24 to 25
A0 to A1
Address Inputs. Used to select one of four analog input channels in combination with CS and WR. The address inputs are
latched on the rising edge of WR or CS.
A1
A0
Selected Channel
LOW
LOW
HIGH
HIGH
LOW
HIGH
LOW
HIGH
AIN0
AIN1
AIN2
AIN3
26
CAL
Calibration Input. A calibration cycle is initiated when CAL is LOW. The minimum pulse width of CAL is 100ns. If not used,
connect to VD. In this case calibration is only initiated at power on, or with SFR. This pin has an internal pull-up.
27
28
AGND
VA
Analog Ground. AGND = 0V.
Analog Supply. V = +5V. Must be ≥ VD and VREF+.
A
®
ADC7802
4
BB [ BURR-BROWN CORPORATION ]
