AV-51001
2015.12.21
5
Arria V Device Variants and Packages
Feature
Description
Configuration
•
Tamper protection-comprehensive design protection to protect your valuable IP
investments
•
•
•
•
Enhanced advanced encryption standard (AES) design security features
CvP
Partial and dynamic reconfiguration of the FPGA
Active serial (AS) x1 and x4, passive serial (PS), JTAG, and fast passive parallel
(FPP) x8, x16, and x32 ( Arria V GZ) configuration options
Remote system upgrade
•
Arria V Device Variants and Packages
Table 3: Device Variants for the Arria V Device Family
Variant
Description
Arria V GX
FPGA with integrated 6.5536 Gbps transceivers that provides bandwidth, cost, and
power levels that are optimized for high-volume data and signal-processing applica‐
tions
Arria V GT
Arria V GZ
FPGA with integrated 10.3125 Gbps transceivers that provides enhanced high-speed
serial I/O bandwidth for cost-sensitive data and signal processing applications
FPGA with integrated 12.5 Gbps transceivers that provides enhanced high-speed serial
I/O bandwidth for high-performance and cost-sensitive data and signal processing
applications
Arria V SX
Arria V ST
SoC with integrated ARM-based HPS and 6.5536 Gbps transceivers
SoC with integrated ARM-based HPS and 10.3125 Gbps transceivers
Arria V GX
This section provides the available options, maximum resource counts, and package plan for the
Arria V GX devices.
The information in this section is correct at the time of publication. For the latest information and to get
more details, refer to the Altera Product Selector.
Related Information
Altera Product Selector
Provides the latest information about Altera products.
Arria V Device Overview
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