AV-51001
2015.12.21
9
Package Plan
D7
Member Code
Resource
C3
3 (9)
4
C7
6 (24)
12
D3
6 (24)
12
6 Gbps(4)
10 Gbps(5)
6 (36)
Transceiver
GPIO(6)
20
704
160
176
2
416
68
80
1
544
120
136
2
704
160
176
2
Transmitter
Receiver
LVDS
PCIe Hard IP Block
Hard Memory Controller
2
4
4
4
Related Information
•
High-Speed Differential I/O Interfaces and DPA in Arria V Devices chapter, Arria V Device
Handbook
Provides the number of LVDS channels in each device package.
Transceiver Architecture in Arria V Devices
•
Describes 10 Gbps channels usage conditions and SFF-8431 compliance requirements.
Package Plan
Table 7: Package Plan for Arria V GT Devices
F672
F896
(31 mm)
XCVR
10-
Gbps Gbps
F1152
F1517
(27 mm)
(35 mm)
(40 mm)
Memb
er
XCVR
10-
XCVR
10-
XCVR
Code
GPIO
GPIO
GPIO
GPIO
6-
Gbps Gbps
6-
6-
Gbps Gbps
6-
Gbps
10-Gbps
C3
C7
D3
D7
336
—
3 (9)
—
4
416
3 (9)
4
8
—
—
—
12
12
12
—
—
—
—
—
—
12
20
—
—
—
384 6 (18)
384 6 (18)
544 6 (24)
544 6 (24)
544 6 (24)
—
—
8
704 6 (24)
704 6 (36)
—
—
—
—
—
The 6-Gbps transceiver counts are for dedicated 6-Gbps channels. You can also configure any pair of 10-
Gbps channels as three 6-Gbps channels—the total number of 6-Gbps channels are shown in brackets.
For example, you can also configure the Arria V GT D7 device in the F1517 package with nine 6-Gbps
(4)
The 6 Gbps transceiver counts are for dedicated 6-Gbps channels. You can also configure any pair of
10 Gbps channels as three 6 Gbps channels-the total number of 6 Gbps channels are shown in brackets.
Chip-to-chip connections only. For 10 Gbps channel usage conditions, refer to the Transceiver Architecture
in Arria V Devices chapter.
The number of GPIOs does not include transceiver I/Os. In the Quartus Prime software, the number of user
I/Os includes transceiver I/Os.
(5)
(6)
Arria V Device Overview
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