AV-51001
2015.12.21
3
Summary of Arria V Features
Feature
Description
Variable-precision
DSP
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Native support for up to four signal processing precision
levels:
•
Three 9 x 9, two 18 x 18, or one 27 x 27 multiplier in the
same variable-precision DSP block
•
One 36 x 36 multiplier using two variable-precision DSP
blocks ( Arria V GZ devices only)
64-bit accumulator and cascade for systolic finite impulse
responses (FIRs)
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•
Embedded internal coefficient memory
Preadder/subtractor for improved efficiency
Memory controller DDR3 and DDR2
( Arria V GX, GT,
SX, and ST only)
Embedded Hard IP
blocks
Embedded
transceiver I/O
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•
Custom implementation:
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•
Arria V GX and SX devices—up to 6.5536 Gbps
Arria V GT and ST devices—up to 10.3125 Gbps
Arria V GZ devices—up to 12.5 Gbps
PCI Express® (PCIe®) Gen2 (x1, x2, or x4) and Gen1 (x1, x2,
x4, or x8) hard IP with multifunction support, endpoint,
and root port
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•
PCIe Gen3 (x1, x2, x4, or x8) support ( Arria V GZ only)
Gbps Ethernet (GbE) and XAUI physical coding sublayer
(PCS)
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•
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Common Public Radio Interface (CPRI) PCS
Gigabit-capable passive optical network (GPON) PCS
10-Gbps Ethernet (10GbE) PCS ( Arria V GZ only)
Serial RapidIO® (SRIO) PCS
Interlaken PCS ( Arria V GZ only)
Clock networks
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Up to 650 MHz global clock network
Global, quadrant, and peripheral clock networks
Clock networks that are not used can be powered down to reduce dynamic power
Phase-locked loops
(PLLs)
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High-resolution fractional PLLs
Precision clock synthesis, clock delay compensation, and zero delay buffering
(ZDB)
•
•
Integer mode and fractional mode
LC oscillator ATX transmitter PLLs ( Arria V GZ only)
Arria V Device Overview
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