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5ASXFB5H4F40I3N 参数 Datasheet PDF下载

5ASXFB5H4F40I3N图片预览
型号: 5ASXFB5H4F40I3N
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 670MHz, PBGA1517, ROHS COMPLIANT, FBGA-1517]
分类和应用: 可编程逻辑
文件页数/大小: 40 页 / 886 K
品牌: ALTERA [ ALTERA CORPORATION ]
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AV-51001  
2015.12.21  
4
Summary of Arria V Features  
Feature  
Description  
FPGA General-  
purpose I/Os  
(GPIOs)  
1.6 Gbps LVDS receiver and transmitter  
800 MHz/1.6 Gbps external memory interface  
On-chip termination (OCT)  
3.3 V support (2)  
External Memory Memory interfaces with low latency:  
Interface  
Hard memory controller-up to 1.066 Gbps  
Soft memory controller-up to 1.6 Gbps  
Low-power high-  
speed serial interface  
600 Mbps to 12.5 Gbps integrated transceiver speed  
Less than 105 mW per channel at 6 Gbps, less than 165 mW per channel at  
10 Gbps, and less than 170 mW per channel at 12.5 Gbps  
Transmit pre-emphasis and receiver equalization  
Dynamic partial reconfiguration of individual channels  
Physical medium attachment (PMA) with soft PCS that supports 9.8304 Gbps  
CPRI ( Arria V GT and ST only)  
PMA with hard PCS that supports up to 9.8 Gbps CPRI ( Arria V GZ only)  
Hard PCS that supports 10GBASE-R and 10GBASE-KR ( Arria V GZ only)  
HPS  
Dual-core ARM Cortex-A9 MPCore processor—up to 1.05 GHz maximum  
frequency with support for symmetric and asymmetric multiprocessing  
Interface peripherals—10/100/1000 Ethernet media access control (EMAC),  
USB 2.0 On-The-GO (OTG) controller, quad serial peripheral interface (QSPI)  
flash controller, NAND flash controller, Secure Digital/MultiMediaCard (SD/  
MMC) controller, UART, serial peripheral interface (SPI), I2C interface, and up to  
85 HPS GPIO interfaces  
( Arria V SX and ST  
devices only)  
System peripherals—general-purpose timers, watchdog timers, direct memory  
access (DMA) controller, FPGA configuration manager, and clock and reset  
managers  
On-chip RAM and boot ROM  
HPS–FPGA bridges—include the FPGA-to-HPS, HPS-to-FPGA, and lightweight  
HPS-to-FPGA bridges that allow the FPGA fabric to issue transactions to slaves in  
the HPS, and vice versa  
FPGA-to-HPS SDRAM controller subsystem—provides a configurable interface to  
the multiport front end (MPFE) of the HPS SDRAM controller  
ARM CoreSightJTAG debug access port, trace port, and on-chip trace storage  
(2)  
Arria V GZ devices support 3.3 V with a 3.0 V VCCIO  
.
Arria V Device Overview  
Send Feedback  
Altera Corporation