MAX 5000 Programmable Logic Device Family Data Sheet
In the array clocking mode, each flipflop is clocked by a product term.
Any input pin or internal logic can be used as a clock source. Array
clocking allows each flipflop to be configured for positive- or negative-
edge-triggered operation, giving the macrocell increased flexibility.
Systems that require multiple clocks are easily integrated into MAX 5000
EPLDs.
Each flipflop in an LAB can be clocked by a different array-generated
clock; however, global and array clocking modes cannot be mixed in the
same LAB.
Expander Product Terms
While most logic functions can be implemented with the product terms
available in each macrocell, some logic functions are more complex and
require additional product terms. Although additional macrocells can be
used to supply the needed logic resources, the MAX 5000 architecture can
also use shared expander product terms that provide additional product
terms directly to any macrocell in the same LAB. These expanders help
ensure that logic is synthesized with the fewest possible logic resources to
obtain the fastest possible speed.
Each LAB has 32 shared expanders (except for EPM5032 devices, which
have 64). The expanders can be viewed as a pool of uncommitted product
terms. The expander product-term array (see Figure 3) contains
unallocated, inverted product terms that feed the macrocell array.
Expanders can be used and shared by all product terms in the LAB.
Wherever extra logic is needed (including register control functions),
expanders can be used to implement the logic. These expanders provide
the flexibility to implement register- and product-term-intensive designs
in MAX 5000 EPLDs.
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