MAX 5000 Programmable Logic Device Family Data Sheet
Table 3. MAX 5000 Pin Count & Package Options
Device
Pin Count
PLCC
CerDIP
PDIP
PGA
PQFP
EPM5032
EPM5064
EPM5128
EPM5130
EPM5192
28
28
28
44
68
84
84
68
100
84
100
MAX 5000 EPLDs have between 32 and 192 macrocells that are combined
into groups called logic array blocks (LABs). Each macrocell has a
programmable-AND/fixed-ORarray and a configurable register that
provides D, T, JK, or SR operation with independent programmable clock,
clear, and preset functions. To build complex logic functions, each
macrocell can be supplemented with shareable expander product terms
(“shared expanders”) to provide more than 32 product terms per
macrocell.
The MAX 5000 family is supported by Altera’s MAX+PLUS II
development system, a single, integrated package that offers schematic,
text—including the Altera Hardware Description Language (AHDL)—
and waveform design entry, compilation and logic synthesis, simulation
and timing analysis, and device programming. The MAX+PLUS II system
provides EDIF 2 0 0 and 3 0 0, LPM, VHDL, Verilog HDL, and other
interfaces for additional design entry and simulation support from other
industry-standard PC- and UNIX workstation-based EDA tools. The
MAX+PLUS II software runs on Windows-based PCs as well as Sun
SPARCstation, HP 9000 Series 700/800, and IBM RISC System/6000
workstations.
9
For more information on the MAX+PLUS II development system, see the
MAX+PLUS II Programmable Logic Development System & Software Data
Sheet.
f
This section provides a functional description of MAX 5000 EPLDs, which
have the following architectural features:
Functional
Description
■
■
■
■
■
■
Logic array blocks
Macrocells
Clocking options
Expander product terms
Programmable interconnect array
I/O control blocks
Altera Corporation
711
ALTERA [ ALTERA CORPORATION ]
