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5962-9206201MYX 参数 Datasheet PDF下载

5962-9206201MYX图片预览
型号: 5962-9206201MYX
PDF下载: 下载PDF文件 查看货源
内容描述: [UV PLD, 90ns, 192-Cell, CMOS, CPGA84, CERAMIC, PGA-84]
分类和应用: 时钟输入元件可编程逻辑
文件页数/大小: 41 页 / 837 K
品牌: ALTERA [ ALTERA CORPORATION ]
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MAX 5000 Programmable Logic Device Family Data Sheet  
Figure 3. Expander Product Terms  
To Macrocell Array  
8 or 20  
Dedicated  
Inputs  
24 Programmable  
Interconnect Signals  
(Multi-LAB Devices Only)  
32 or 64  
Expander  
Product Terms  
Macrocell  
Feedbacks  
Expanders are fed by all signals in the LAB. One expander can feed all  
macrocells in the LAB or multiple product terms in the same macrocell.  
Because expanders also feed the secondary product terms of each  
macrocell, complex logic functions can be implemented without using  
additional macrocells. A small delay (tSEXP) is incurred when shared  
expanders are used.  
Programmable Interconnect Array  
The multi-LAB MAX 5000 devices—EPM5064, EPM5128, EPM5130, and  
EPM5192 devices—use a PIA to route signals between the various LABs.  
The PIA, which is fed by all macrocell and I/O pin feedbacks, routes only  
the signals required for implementing logic in an LAB. While the routing  
delays of segmented routing schemes in masked or field-programmable  
gate arrays (FPGAs) are cumulative, variable, and path-dependent, the  
MAX 5000 PIA has a fixed delay. The PIA thus eliminates skew between  
signals and makes timing performance easy to predict.  
I/O Control Blocks  
Each LAB has an I/O control block that allows each I/O pin to be  
individually configured for input, output, or bidirectional operation (see  
Figure 4). The I/O control block is fed by the macrocell array. A dedicated  
macrocell product term controls a tri-state buffer, which drives the I/O  
pin.  
716  
Altera Corporation