MAX 5000 Programmable Logic Device Family Data Sheet
Figure 4. I/O Control Block
OE Control (from Macrocell Product)
From Macrocell
Macrocell Feedback
I/O Pin Feedback
The MAX 5000 architecture provides dual I/O feedback in which
macrocell and I/O pin feedbacks are independent, allowing maximum
flexibility. When an I/O pin is configured as an input, the associated
macrocell can be used for buried logic. Using an I/O pin as an input in
single-LAB devices reduces the number of available expanders by two. In
multi-LAB devices, I/O pins feed the PIA directly.
All MAX 5000 EPLDs contain a programmable security bit that controls
access to the data programmed into the device. When this bit is
programmed, a proprietary design implemented in the device cannot be
copied or retrieved. This feature provides a high level of design security,
because programmed data within EPROM cells is invisible. The security
bit that controls this function, as well as all other program data, is reset
only when the device is erased.
Design Security
Generic Testing
MAX 5000 EPLDs are fully functionally tested. Complete testing of each
programmable EPROM bit and all internal logic elements ensures 100%
programming yield. Test patterns can be used and then erased during
early stages of the device production flow. The devices also contain
on-board logic test circuitry to allow verification of function and AC
specifications during the production flow. AC test measurements are
taken under conditions equivalent to those in Figure 5.
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Altera Corporation
717
ALTERA [ ALTERA CORPORATION ]
