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VT82C686B 参数 Datasheet PDF下载

VT82C686B图片预览
型号: VT82C686B
PDF下载: 下载PDF文件 查看货源
内容描述: PCI SUPER -I / O集成外设控制器 [PCI Super-I/O Integrated Peripheral Controller]
分类和应用: 控制器PC
文件页数/大小: 128 页 / 1074 K
品牌: ETC [ ETC ]
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VT82C686B  
Offset 58 GP2 / GP3 Timer Control .............................RW  
Offset 59 GP2 Timer...................................................... RW  
...............default = 0  
7
GP3 Timer Start  
7
Write: GP2 Timer Load Value  
On setting this bit to 1, the GP3 timer loads the value  
defined by Rx5A and starts counting down. The GP3  
timer is reloaded at the occurrence of certain events  
enabled in the GP Timer Reload Enable Register  
(Power Management I/O Space Offset 38h). If no  
such event occurs and the GP3 timer counts down to  
zero, then the GP3 Timer Timeout Status bit is set to  
one (bit-13 of the Global Status register at Power  
Management Register I/O Space Offset 28h).  
Additionally, if the GP3 Timer Timeout Enable bit is  
set (bit-13 of the Global Enable register at Power  
Management Register I/O Space Offset 2Ah), then an  
SMI is generated.  
Read: GP2 Timer Current Count  
Offset 5A GP3 Timer..................................................... RW  
...............default = 0  
7
Write: GP3 Timer Load Value  
Read: GP3 Timer Current Count  
6
GP3 Timer Automatic Reload  
0
1
GP3 Timer stops at 0 .............................default  
Reload GP3 timer automatically after counting  
down to 0  
5-4 GP3 Timer Tick Select  
00 Disable ...................................................default  
01 1/16 second  
10 1 second  
11 1 minute  
3
GP2 Timer Start  
On setting this bit to 1, the GP2 timer loads the value  
defined by Rx59 and starts counting down. The GP2  
timer is reloaded at the occurrence of certain events  
enabled in the GP Timer Reload Enable Register  
(Power Management I/O Space Offset 38h). If no  
such event occurs and the GP2 timer counts down to  
zero, then the GP2 Timer Timeout Status bit is set to  
one (bit-12 of the Global Status register at Power  
Management Register I/O Space Offset 28h).  
Additionally, if the GP2 Timer Timeout Enable bit is  
set (bit-12 of the Global Enable register at Power  
Management Register I/O Space Offset 2Ah), then an  
SMI is generated.  
2
GP2 Timer Automatic Reload  
0
1
GP2 Timer stops at 0 .............................default  
Reload GP2 timer automatically after counting  
down to 0  
1-0 GP2 Timer Tick Select  
00 Disable ...................................................default  
01 1/16 second  
10 1 second  
11 1 minute  
Revision 1.71 June 9, 2000  
-87-  
Function 4 Regs - Power Management, SMBus and HWM  
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