VT82C686B
Offset 54 – Power Well Control ...................................... WO
Offset 55 – USB Wakeup.................................................. RW
........................................always reads 0
Deassert SUSST1# Before PWRGD Rising for S5
Wakeup
7
6
5
4
3
SMBus Clock Select
7-3 Reserved
2
0
SMBus Clock from 14.31818 MHz Divider def
1
SMBus Clock from RTC 32.768 KHz
0
Disable................................................... default
STR Power Well Output Gating
0
Disable ...................................................default
1
Enable
1
Enable
........................................always reads 0
USB Wakeup for STR/STD/Soff
1
0
Reserved
SUSC# = 0 for STR
0
Disable ...................................................default
0
Disable................................................... default
1
Enable
1
Enable
SUSST1# / GPO3 Select (Pin V10)
0
SUSST1#................................................default
1
GPO3
Offset 57 – Miscellaneous Control................................... RW
GPO2 / SUSB# Select (Pin W9)
........................................always reads 0
Internal THRM# Output on GPO21
7-1 Reserved
0
0
SUSB#....................................................default
1
GPO2
0
Disable................................................... default
Before chip rev C, this definition was reversed
See also Function 0 Rx74[7] and 77[4]
GPO1 / SUSA# Select (Pin V9)
1
Enable
2
0
SUSA# ...................................................default
1
GPO1
Before chip rev C, this definition was reversed
See also Function 0 Rx74[7] and 77[4]
1-0 GPO0 (SLOWCLK) Output Selection (Pin T8)
00 From GPO0 (PMU I/O Rx4C[0])...........default
01 1 Hz
10 4 Hz
11 16 Hz
Revision 1.71 June 9, 2000
-86-
Function 4 Regs - Power Management, SMBus and HWM
ETC [ ETC ]
