VT82C686B
Offset 46 - Miscellaneous Control 1.................................RW
Offset 47 - Miscellaneous Control 2 ................................ RW
7
6
5
4
PCI Master Write Wait States
7
CPU Reset Source
0
0 Wait States ..........................................default
0
Use CPURST as CPU Reset.................. default
1
1 Wait State
1
Use INIT as CPU Reset
Gate INTR
6
PCI Delay Transaction Enable
0
Disable ...................................................default
0
Disable................................................... default
1
Enable
1
Enable
The "Posted Memory Write" function is
automatically enabled when this bit is enabled,
independent of the state of Rx46 bit-0.
Flush Line Buffer for Int or DMA IOR Cycle
0
Disable ...................................................default
1
Enable
Config Command Reg Rx04 Access (Test Only)
5
4
EISA 4D0/4D1 Port Enable
0
Normal: Bits 0-1=RO, Bit 3=RW..........default
0
Disable (ignore ports 4D0-1)................. default
1
Test Mode: Bits 0-1=RW, Bit-3=RO
1
Enable (ports 4D0-1 per EISA specification)
(do not program)........................ default = 0
(no function).............................. default = 0
3
2
1
Reserved
Reserved
Interrupt Controller Shadow Register Enable
0
1
Disable................................................... default
Enable (for test purposes, enable readback of
interrupt controller internal functions on I/O
reads from ports 20-21, A0-A1, A8-A9, and
C8-C9) (Contact VIA Test Engineering
department)
PCI Burst Read Interruptability
0
1
Allow burst reads to be interrupted by ISA
master or DMA.......................................default
Don’t allow PCI burst reads to be interrupted
0
Posted Memory Write Enable
0
Disable ...................................................default
..............default = 0
Reserved (always program to 0)
3
1
Enable
Note: Always mask this bit. This bit may read back
as either 0 or 1 but must always be
programmed with 0.
The Posted Memory Write function is automatically
enabled when Delay Transaction (see Rx47 bit-6) is
enabled, independent of the state of this bit.
2
1
0
Write Delay Transaction Time-Out Timer
0
Disable................................................... default
1
Enable
Read Delay Transaction Time-Out Timer
0
Disable................................................... default
1
Enable
......write 1 to generate PCI reset
Software PCI Reset
Revision 1.71 June 9, 2000
-57-
Function 0 Registers - PCI to ISA Bridge
ETC [ ETC ]
