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VT82C686B 参数 Datasheet PDF下载

VT82C686B图片预览
型号: VT82C686B
PDF下载: 下载PDF文件 查看货源
内容描述: PCI SUPER -I / O集成外设控制器 [PCI Super-I/O Integrated Peripheral Controller]
分类和应用: 控制器PC
文件页数/大小: 128 页 / 1074 K
品牌: ETC [ ETC ]
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VT82C686B  
Super-I/O I/O Ports  
Floppy Disk Controller Registers  
These registers are located at I/O ports which are offsets from  
FDCBase(index E3h of the Super-I/O configuration  
registers). FDCBase is typically set to allow these ports to be  
accessed at the standard floppy disk controller address range  
of 3F0-3F7h.  
Port FDCBase+2 FDC Command.................................RW  
Port FDCBase+4 FDC Data Rate Select......................WO  
7
6
5
Motor 3 (unused in VT82C686B: no MTR3# pin)  
Motor 2 (unused in VT82C686B: no MTR2# pin)  
Motor 1  
7
6
5
Software Reset  
0
Normal operation................................... default  
1
Execute FDC reset (this bit is self clearing)  
0
Motor Off  
Power Down  
1
Motor On  
0
1
Normal operation................................... default  
Power down FDC logic  
........................................always reads 0  
4
3
2
Motor 0  
0
Motor Off  
Reserved  
1
Motor On  
4-2 Precompensation Select  
Selects the amount of write precompensation to be  
used on the WDATA output:  
000 Default ................................................... default  
001 41.7 ns  
DMA and IRQ Channels  
0
Disable  
1
Enable  
FDC Reset  
0
Execute FDC Reset  
010 93.3 ns  
1
FDC Enable  
011 125.0 ns  
1-0 Drive Select  
00 Select Drive 0  
100 166.7 ns  
101 208.3 ns  
01 Select Drive 1  
1x -reserved-  
110 250.0 ns  
111 0.0 ns (disable)  
1-0 Data Rate  
Port FDCBase+4 FDC Main Status...............................RO  
MFM FM  
Drive Type  
7
6
5
4
Main Request  
00 500K 250K bps 1.2MB 5or 1.44 MB 3”  
01 300K 150K bps 360KB 5”  
10 250K 125K bps 720KB 3................ default  
0
Data register not ready  
1
Data register ready  
Data Input / Output  
11  
1M illegalbps  
0
CPU => FDC  
Note: these bits are not changed by software reset  
1
FDC => CPU  
Port FDCBase+5 FDC Data.......................................... RW  
Non-DMA Mode  
0
FDC in DMA mode  
Port FDCBase+7 FDC Disk Change Status................. RW  
1
FDC not in DMA mode  
7
Disk Change......................................................... RO  
FDC Busy  
0
Floppy not changed................................ default  
0
FDC inactive  
FDC active  
........................................ always reads 0  
Drive 1 Active  
1
Floppy changed since last instruction  
1
..................................... always reads 1s  
6-2 Undefined  
3-2 Reserved  
1-0 Data Rate ........................................................WO  
00 500 Kbit/sec (1.2MB 5or 1.44 MB 3drive)  
01 300 Kbit/sec (360KB 5drive)  
1
0
Drive inactive  
1
Drive performing a positioning change  
10 250 Kbit/sec (720KB 3drive)  
0
Drive 0 Active  
11 1 Mbit/sec  
0
Drive inactive  
1
Drive performing a positioning change  
Revision 1.71 June 9, 2000  
-48-  
Register Descriptions - Super-I/O I/O Ports  
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