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VT82C686B 参数 Datasheet PDF下载

VT82C686B图片预览
型号: VT82C686B
PDF下载: 下载PDF文件 查看货源
内容描述: PCI SUPER -I / O集成外设控制器 [PCI Super-I/O Integrated Peripheral Controller]
分类和应用: 控制器PC
文件页数/大小: 128 页 / 1074 K
品牌: ETC [ ETC ]
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VT82C686B  
Parallel Port Registers  
These registers are located at I/O ports which are offsets from  
LPTBase(index E6h of the Super-I/O configuration  
registers). LPTBase is typically set to allow these ports to be  
accessed at the standard parallel port address range of 378-  
37Fh.  
Port LPTBase+0 Parallel Port Data .............................RW  
Port LPTBase+3 Parallel Port EPP Address............... RW  
Port LPTBase+4 Parallel Port EPP Data Port 0......... RW  
Port LPTBase+5 Parallel Port EPP Data Port 1......... RW  
Port LPTBase+6 Parallel Port EPP Data Port 2......... RW  
Port LPTBase+7 Parallel Port EPP Data Port 3......... RW  
7-0 Parallel Port Data  
Port LPTBase+1 Parallel Port Status............................RO  
7
6
5
4
3
BUSY#  
0
Printer busy, offline, or error  
1
Printer not busy  
ACK#  
0
Data transfer to printer complete  
1
Data transfer to printer in progress  
PE  
0
Paper available  
Port LPTBase+400h Parallel Port ECP Data / Cfg A RW  
Port LPTBase+401h Parallel Port ECP Config B....... RW  
Port LPTBase+402h Parallel Port ECP Extd Ctrl...... RW  
1
No paper available  
SLCT  
0
1
Printer offline  
Printer online  
7-5 Parallel Port Mode Select  
000 Standard Mode....................................... default  
001 PS/2 Mode  
ERROR#  
0
1
Printer error  
Printer OK  
................................... always read 1 bits  
010 FIFO Mode  
2-0 Reserved  
011 ECP Mode  
100 EPP Mode  
101 -reserved-  
110 -reserved-  
111 Configuration Mode  
Parallel Port Interrupt Disable  
Port LPTBase+2 Parallel Port Control ........................RW  
................................. always read back 1  
7-5 Undefined  
4
3
2
1
0
Hardware Interrupt  
4
0
Disable ...................................................default  
0
1
Enable an interrupt pulse to be generated on  
the high to low edge of the fault. An interrupt  
will also be generated if the fault condition is  
asserted and this bit is written from 1 to 0.  
Disable the interrupt generated on the asserting  
edge of the fault condition  
1
Enable  
Printer Select  
0
Deselect printer ......................................default  
1
Select printer  
Printer Initialize  
0
Initialize Printer......................................default  
3
2
Parallel Port DMA Enable  
1
Allow printer to operate normally  
0
Disable DMA unconditionally  
Automatic Line Feed  
1
Enable DMA  
0
Host handles line feeds...........................default  
Parallel Port Interrupt Pending  
1
Printer does automatic line feeds  
0
Interrupt not pending  
Strobe  
1
Interrupt pending (DMA & interrupts disabled)  
0
No data transfer......................................default  
This bit is set to 1 by hardware and must be written to  
0 to re-enable interrupts  
1
Transfer data to printer  
1
0
FIFO Full ......................................................... RO  
0
FIFO has at least 1 free byte  
1
FIFO full or cannot accept byte  
FIFO Empty......................................................... RO  
0
FIFO contains at least 1 byte of data  
1
FIFO is completely empty  
Revision 1.71 June 9, 2000  
-49-  
Register Descriptions - Super-I/O I/O Ports  
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