VT82C686B
Serial Port 2 Registers
Port COM2Base+4 – Handshake Control ...................... RW
......................................... always read 0
Loopback Check
7-5 Undefined
4
These registers are located at I/O ports which are offsets from
“COM2Base” (index E8h of the Super-I/O configuration
registers). COM2Base is typically set to allow these ports to
be accessed at the standard serial port 2 address range of 2F8-
2FFh.
0
Normal operation
1
Loopback enable
3
2
1
General Purpose Output 2 (unused in 82C686B)
General Purpose Output 1 (unused in 82C686B)
Request To Send
Port COM2Base+0 – Transmit / Receive Buffer ............RW
0
Disable
7-0 Serial Data
1
Enable
Port COM2Base+1 – Interrupt Enable ...........................RW
0
Data Terminal Ready
..........................................always read 0
7-4 Undefined
0
Disable
3
2
1
0
Interrupt on Handshake Input State Change
Intr on Parity, Overrun, Framing Error or Break
Interrupt on Transmit Buffer Empty
1
Enable
Port COM2Base+5 – UART Status................................. RW
......................................... always read 0
Transmitter Empty
7
6
Undefined
Interrupt on Receive Data Ready
Port COM2Base+1-0 – Baud Rate Generator Divisor...RW
0
1 byte in transmit hold or transmit shift register
15-0 Divisor Value for Baud Rate Generator
Baud Rate = 115,200 / Divisor
1
0 bytes transmit hold and transmit shift regs
5
4
3
2
1
0
Transmit Buffer Empty
(e.g., setting this register to 1 selects 115.2 Kbaud)
0
1
1 byte in transmit hold register
Transmit hold register empty
Port COM2Base+2 – Interrupt Status .............................RO
Break Detected
..........................................always read 0
(0=highest priority)
7-3 Undefined
2-1 Interrupt ID
0
1
No break detected
Break detected
00 Priority 3 (Handshake Input Changed State)
01 Priority 2 (Transmit Buffer Empty)
10 Priority 1 (Data Received)
Framing Error Detected
0
1
No error
Error
11 Priority 0 (Serialization Error or Break)
Parity Error Detected
0
Interrupt Pending
0
1
No error
Error
0
1
Interrupt Pending
No Interrupt Pending
Overrun Error Detected
0
1
No error
Error
Port COM2Base+2 – FIFO Control ............................... WO
Received Data Ready
Port COM2Base+3 – UART Control...............................RW
0
1
No received data available
Received data in receiver buffer register
7
6
Divisor Latch Access
0
Access xmit / rcv & int enable regs at 0-1
1
Access baud rate generator divisor latch at 0-1
Port COM2Base+6 – Handshake Status......................... RW
Break
7
6
5
4
3
2
1
0
DCD Status (1=Active, 0=Inactive)
RI Status (1=Active, 0=Inactive)
DSR Status (1=Active, 0=Inactive)
CTS Status (1=Active, 0=Inactive)
DCD Changed (1=Changed Since Last Read)
RI Changed (1=Changed Since Last Read)
DSR Changed (1=Changed Since Last Read)
CTS Changed (1=Changed Since Last Read)
0
1
Break condition off
Break condition on
5-3 Parity
000 None
001 Odd
011 Even
101 Mark
111 Space
Stop Bits
2
Port COM2Base+7 – Scratchpad.................................... RW
Scratchpad Data
0
1
7
1
2
1-0 Data Bits
00 5
01 6
10 7
11 8
Revision 1.71 June 9, 2000
-51-
Register Descriptions - Super-I/O I/O Ports
ETC [ ETC ]
