Power Driver Integrated Full Digital Audio Amplifier
NTP-8230
(a)
P
Data (Byte #1) NAK
S
Slave address
Slave address
W
A AIF Subaddress
A AIF Subaddress
A
Sr
Sr
Slave address
Slave address
R
A
Data (Byte #4)
A
Data (Byte #3)
A
Data (Byte #2)
A
(b)
S
W
A
R
A
Data #1 (Byte #4)
A
Data #1 (Byte #3)
A
Data #1 (Byte #2)
A
Data #1 (Byte #1)
Data #n-1 (Byte #4)
A
Data #n (Byte #4)
A
Data #n(Byte #3)
A
Data #n (Byte #2)
A
Data #n (Byte #1)
A
Figure 9. Quad Byte Read Mode Sequence
In read operation, the register 0x7E value needs to be set first for performing the configuration of the
registers belong to all channels. The 0x7E register also support to configuring byte reads operation
and word i.e. 4 byte reads operation.
If 0x7E register is configure to 0x00, it support byte read operation and for word i.e. 4 byte read
operation for each channel it needs to configure as 0x01 for channel 1, 0x02 for channel 2, 0x04 for
channel 3 and 0x08 for PEQ. Also to configure channel1 and channel2 with the same values, the 0x7E
register needs to configure as 0x03. So the same values get sets for both the channel with only one
read operation.
5.1.3. I2C Glitch Filter
To clean out the threats of noise in today‟s high-speed-board system, the NTP-8230 has a glitch
elimination filter on the I2C ports. Glitches in the transmission lines of the I2C port can be safely
removed with this function. Please refer to the register 0x3A.
Copyright ⓒ NeoFidelity, Inc.
Page 13
Document Number: DS8230 draft ver. 0.1
2011-01-11
ETC [ ETC ]
