LHF80V25
21
sharp
A system designer must guard against spurious writes for
voltages above V when V is active. Since both
WE# and CE# must be low for a command write, driving
5.5 V , V , RP# Transitions
CC PP
V
CC
LKO
PP
Block erase and word/byte write are not guaranteed if V
PP
either to V will inhibit writes. The CUI’s two-step
falls outside of a valid V
range, V falls outside of
IH
PPH1/2
CC
command sequence architecture provides added level of
protection against data alteration.
a valid 4.5V-5.5V range, or RP#≠V or V . If V error
IH
HH
PP
is detected, status register bit SR.3 is set to "1" along with
SR.4 or SR.5, depending on the attempted operation. If
WP# provide additional protection from inadvertent code
RP# transitions to V during block erase or word/byte
IL
or data alteration. The device is disabled while RP#=V
regardless of its control inputs state.
IL
write, RY/BY# will remain low until the reset operation is
complete. Then, the operation will abort and the device
will enter deep power-down. The aborted operation may
leave data partially altered. Therefore, the command
sequence must be repeated after normal operation is
5.7 Power Dissipation
When designing portable systems, designers must consider
battery power consumption not only during device
operation, but also for data retention during system idle
time. Flash memory’s nonvolatility increases usable
battery life because data is retained when system power is
removed.
restored. Device power-off or RP# transitions to V clear
the status register.
IL
The CUI latches commands issued by system software and
is not altered by V or CE# transitions or WSM actions.
PP
Its state is read array mode upon power-up, after exit from
deep power-down or after V transitions below V
.
CC
LKO
In addition, deep power-down mode ensures extremely
low power consumption even when system power is
applied. For example, portable computing products and
other power sensitive applications that use an array of
devices for solid-state storage can consume negligible
After block erase or word/byte write, even after V
PP
transitions down to V
, the CUI must be placed in read
PPLK
array mode via the Read Array command if subsequent
access to the memory array is desired.
power by lowering RP# to V standby or sleep modes. If
IL
access is again needed, the devices can be read following
5.6 Power-Up/Down Protection
the t
and t
wake-up cycles required after RP# is
PHQV
PHWL
first raised to V . See AC Characteristics− Read Only
IH
The device is designed to offer protection against
accidental block erasure or word/byte writing during
power transitions. Upon power-up, the device is
and Write Operations and Figures 11, 12, 13 and 14 for
more information.
indifferent as to which power supply (V
or V
)
PP
CC
powers-up first. Internal circuitry resets the CUI to read
array mode at power-up.
Rev. 1.1
ETC [ ETC ]
