LHF80V25
13
sharp
4.6 Word/Byte Write Command
4.7 Block Erase Suspend Command
Word/byte write is executed by a two-cycle command
sequence. Word/byte write setup (standard 40H or
alternate 10H) is written, followed by a second write that
specifies the address and data (latched on the rising edge
of WE#). The WSM then takes over, controlling the
word/byte write and write verify algorithms internally.
After the word/byte write sequence is written, the device
automatically outputs status register data when read (see
Figure 6). The CPU can detect the completion of the
word/byte write event by analyzing the RY/BY# pin or
status register bit SR.7.
The Block Erase Suspend command allows block-erase
interruption to read or word/byte write data in another
block of memory. Once the block-erase process starts,
writing the Block Erase Suspend command requests that
the WSM suspend the block erase sequence at a
predetermined point in the algorithm. The device outputs
status register data when read after the Block Erase
Suspend command is written. Polling status register bits
SR.7 and SR.6 can determine when the block erase
operation has been suspended (both will be set to "1").
RY/BY# will also transition to High Z. Specification
t
defines the block erase suspend latency.
WHRZ2
When word/byte write is complete, status register bit SR.4
should be checked. If word/byte write error is detected, the
status register should be cleared. The internal WSM verify
only detects errors for "1"s that do not successfully write
to "0"s. The CUI remains in read status register mode until
it receives another command.
At this point, a Read Array command can be written to
read data from blocks other than that which is suspended.
A Word/Byte Write command sequence can also be issued
during erase suspend to program data in other blocks.
Using the Word/Byte Write Suspend command (see
Section 4.8), a word/byte write operation can also be
suspended. During a word/byte write operation with block
erase suspended, status register bit SR.7 will return to "0"
Reliable word/byte writes can only occur when
V
=4.5V-5.5V and V =V
. In the absence of this
CC
PP
PPH1/2
high voltage, memory contents are protected against
word/byte writes. If word/byte write is attempted while
and the RY/BY# output will transition to V . However,
SR.6 will remain "1" to indicate block erase suspend
status.
OL
V
≤V
, status register bits SR.3 and SR.4 will be set
PP
PPLK
to "1". Successful word/byte write for boot blocks requires
that the corresponding if set, that WP#=V or RP#=V
The only other valid commands while block erase is
suspended are Read Status Register and Block Erase
Resume. After a Block Erase Resume command is written
to the flash memory, the WSM will continue the block
erase process. Status register bits SR.6 and SR.7 will
.
HH
IH
If word/byte write is attempted to boot block when the
corresponding WP#=V or RP#=V , SR.1 and SR.4 will
IL
IH
be set to "1". Word/byte write operations with
V <RP#<V produce spurious results and should not be
IH
HH
automatically clear and RY/BY# will return to V . After
attempted.
OL
the Erase Resume command is written, the device
automatically outputs status register data when read (see
Figure 7). V must remain at V
(the same V
PP
PPH1/2
PP
level used for block erase) while block erase is suspended.
RP# must also remain at V or V (the same RP# level
IH
HH
used for block erase). WP# must also remain at V or V
IL
IH
(the same WP# level used for block erase). Block erase
cannot resume until word/byte write operations initiated
during block erase suspend have completed.
Rev. 1.1
ETC [ ETC ]
