80C186XL/80C188XL
Test Conditions
e
a
0 C to 70 C, V
e
5V 10%
CC
g
DC SPECIFICATIONS (Continued) T
§
§
A
Symbol
Parameter
Clock Output High
Input Capacitance
Min
Max
Units
V
b
e b
500 mA
V
V
0.5
I
CHO
CHO
CC
(2)
@
@
C
C
10
20
pF
1 MHz
1 MHz
IN
IO
(2)
Output or I/O Capacitance
pF
NOTES:
1. Pins being floated during HOLD or by invoking the ONCE Mode.
e
a
5.0V or 0.45V. This
2. Characterization conditions are a) Frequency
parameter is not tested.
3. Current is measured with the device in RESET with X1 and X2 driven and all other non-power pins open.
1 MHz; b) Unmeasured pins at GND; c) V at
IN
4. RD/QSMD, UCS, LCS, MCS0/PEREQ, MCS1/ERROR and TEST/BUSY pins have internal pullup devices. Loading some
e b
Local Bus Controller and Reset for details.
of these pins above I
200 mA can cause the processor to go into alternative modes of operation. See the section on
OH
Power Supply Current
Current is linearly proportional to clock frequency
and is measured with the device in RESET with X1
and X2 driven and all other non-power pins open.
e
c
freq.
Maximum current is given by I
a
5 mA
CC
(MHz)
I
.
QL
I
is the quiescent leakage current when the clock
QL
is static. I is typically less than 100 mA.
QL
272431–9
Figure 5. I vs Frequency
CC
23
ETC [ ETC ]
