80C186XL/80C188XL
AC SPECIFICATIONS (Continued)
MAJOR CYCLE TIMINGS (WRITE CYCLE)
e
a
e
All timings are measured at 1.5V and 50 pF loading on CLKOUT unless otherwise noted.
g
5V 10%
T
0 C to 70 C, V
§
§
A
CC
e
All output test conditions are with C
e
50 pF.
e
L
0.45V and V
e
b
V 0.5V.
CC
For AC tests, input V
2.4V except at X1 where V
IL
IH
IH
Values
Test
Symbol
Parameter
80C186XL25
Min Max
80C186XL GENERAL TIMING RESPONSES (Listed More Than Once)
80C186XL20
80C186XL12
Unit
Conditions
Min
Max
Min
Max
T
T
T
T
T
T
T
T
T
T
Status Active Delay
Status Inactive Delay
Address Valid Delay
Address Hold
3
3
20
20
20
3
3
25
25
27
3
3
35 ns
35 ns
36 ns
ns
CHSV
CLSH
CLAV
CLAX
CLDV
CHDX
CHLH
LHLL
CHLL
AVLL
3
3
3
0
0
0
Data Valid Delay
Status Hold Time
ALE Active Delay
ALE Width
3
20
20
20
3
27
20
20
3
36 ns
ns
10
10
10
25 ns
ns
b
b
b
15
CLCL
T
15
T
15
T
CLCL
CLCL
ALE Inactive Delay
Address Valid to ALE Low
25 ns
ns
b
b
b
b
b
b
T
T
10
10
T
T
10
10
T
T
15
15
Equal
CLCH
CHCL
CLCH
CLCH
Loading
T
Address Hold from ALE
Inactive
ns
Equal
LLAX
CHCL
CHCL
Loading
T
T
T
T
T
T
Address Valid to Clock High
Data Hold Time
0
0
0
ns
ns
AVCH
3
3
3
3
3
3
3
3
3
3
3
3
CLDOX
CVCTV
CVCTX
CLCSV
CXCSX
Control Active Delay 1
Control Inactive Delay
Chip-Select Active Delay
20
17
20
25
25
25
37 ns
37 ns
33 ns
ns
b
b
b
Chip-Select Hold from
Command Inactive
T
10
T
10
T
10
Equal
CLCH
CLCH
CLCH
Loading
T
T
Chip-Select Inactive Delay
DEN Inactive to DT/R Low
3
0
17
17
3
0
20
22
3
0
30 ns
ns
CHCSX
DXDL
Equal
Loading
T
LOCK Valid/Invalid Delay
3
3
3
37 ns
CLLV
80C186XL TIMING RESPONSES (Write Cycle)
b
b
b
b
b
b
T
T
WR Pulse Width
2T
15
14
2T
20
14
2T
25
14
ns
ns
WLWH
WHLH
CLCL
CLCL
CLCL
WR Inactive to ALE High
T
T
CLCH
T
CLCH
Equal
CLCH
Loading
b
b
b
b
b
b
T
T
Data Hold after WR
T
10
10
T
15
10
T
20
10
ns
ns
Equal
WHDX
CLCL
CLCL
CLCL
Loading
WR Inactive to DEN Inactive T
T
CLCH
T
CLCH
Equal
WHDEX
CLCH
Loading
26
ETC [ ETC ]
