80C186XL/80C188XL
Table 4. LCC/PLCC Pin Functions with Location
Bus Control Processor Control
ALE/QS0
AD Bus
I/O
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
17
15
13
11
8
61
64
52
53
54
62
63
55
49
39
40
48
50
51
RES
24
UCS
LCS
34
33
BHE (RFSH)
S0
S1
RESET
X1
X2
57
59
58
56
47
46
45
44
42
41
MCS0/PEREQ
MCS1/ERROR
MCS2
38
37
36
35
S2
CLKOUT
TEST/BUSY
NMI
6
RD/QSMD
WR/QS1
ARDY
SRDY
DEN
4
MCS3/NPS
2
INT0
AD8 (A8)
AD9 (A9)
AD10 (A10)
AD11 (A11)
AD12 (A12)
AD13 (A13)
AD14 (A14)
AD15 (A15)
A16/S3
16
14
12
10
7
INT1/SELECT
INT2/INTA0
INT3/INTA1
PCS0
PCS1
25
27
28
29
30
31
32
DT/R
PCS2
PCS3
LOCK
HOLD
HLDA
PCS4
PCS5/A1
PCS6/A2
Power and Ground
5
V
9
3
CC
CC
SS
SS
V
V
V
43
26
60
1
68
67
66
65
TMR IN 0
TMR IN 1
20
21
22
23
A17/S4
A18/S5
A19/S6
TMR OUT 0
TMR OUT 1
DRQ0
DRQ1
18
19
NOTE:
Pin names in parentheses apply to the 80C188XL.
Table 5. LCC/PGA/PLCC Pin Locations with Pin Names
1
2
AD15 (A15)
AD7
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
DRQ0
DRQ1
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
MCS3/NPS
MCS2
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
S0
S1
3
AD14 (A14)
AD6
TMR IN 0
TMR IN 1
TMR OUT 0
TMR OUT 1
RES
MCS1/ERROR
MCS0/PEREQ
DEN
S2
4
ARDY
CLKOUT
RESET
X2
5
AD13 (A13)
AD5
6
DT/R
INT3/INTA1
INT2/INTA0
7
AD12 (A12)
AD4
8
PCS0
X1
V
SS
9
V
V
SS
PCS1
V
CC
CC
10
11
12
13
14
15
16
17
AD11 (A11)
AD3
INT1/SELECT
INT0
NMI
ALE/QS0
RD/QSMD
WR/QS1
BHE (RFSH)
A19/S2
PCS2
PCS3
PCS4
AD10 (A10)
AD2
TEST/BUSY
LOCK
SRDY
AD9 (A9)
AD1
PCS5/A1
PCS6/A2
LCS
A18/S3
A17/S4
A16/S3
AD8 (A8)
AD0
HOLD
HLDA
UCS
NOTE:
Pin names in parentheses apply to the 80C188XL.
19
ETC [ ETC ]
