80C186XL/80C188XL
AC SPECIFICATIONS
MAJOR CYCLE TIMINGS (READ CYCLE)
e
a
e
All timings are measured at 1.5V and 50 pF loading on CLKOUT unless otherwise noted.
g
5V 10%
T
A
0 C to 70 C, V
§
§
CC
e
All output test conditions are with C
e
50 pF.
e
L
0.45V and V
e
b
V 0.5V.
CC
For AC tests, input V
2.4V except at X1 where V
IL
IH
IH
Values
Test
Symbol
Parameter
80C186XL25
Min Max
80C186XL GENERAL TIMING REQUIREMENTS (Listed More Than Once)
80C186XL20
80C186XL12 Unit
Conditions
Min Max
Min
Max
T
T
Data in Setup (A/D)
Data in Hold (A/D)
8
3
10
3
15
3
ns
ns
DVCL
CLDX
80C186XL GENERAL TIMING RESPONSES (Listed More Than Once)
T
T
T
T
T
T
T
T
T
T
Status Active Delay
Status Inactive Delay
Address Valid Delay
Address Hold
3
3
20
20
20
3
3
25
25
27
3
3
35 ns
35 ns
36 ns
ns
CHSV
CLSH
CLAV
CLAX
CLDV
CHDX
CHLH
LHLL
CHLL
AVLL
3
3
3
0
0
0
Data Valid Delay
Status Hold Time
ALE Active Delay
ALE Width
3
20
20
20
3
27
20
20
3
36 ns
ns
10
10
10
25 ns
ns
b
b
b
15
CLCL
T
15
10
T
15
T
CLCL
CLCH
CLCL
ALE Inactive Delay
Address Valid to ALE Low
25 ns
ns
b
b
b
b
b
T
T
T
10
10
T
T
15
15
Equal
Loading
CLCH
CHCL
CLCH
CHCL
b
T
Address Hold from ALE
Inactive
T
8
ns
Equal
Loading
LLAX
CHCL
T
T
T
T
Address Valid to Clock High
Address Float Delay
0
0
0
ns
25 ns
33 ns
ns
AVCH
CLAZ
T
20
20
T
20
25
T
CLAX
3
CLAX
3
CLAX
3
Chip-Select Active Delay
CLCSV
CXCSX
b
b
b
Chip-Select Hold from
Command Inactive
T
10
T
10
T
10
Equal
Loading
CLCH
CLCH
CLCH
T
T
Chip-Select Inactive Delay
DEN Inactive to DT/R Low
3
17
3
20
3
30 ns
ns
CHCSX
DXDL
0
0
0
Equal
Loading
T
T
T
T
Control Active Delay 1
DEN Inactive Delay
3
3
3
3
17
17
20
17
3
3
3
3
22
22
22
22
3
3
3
3
37 ns
37 ns
37 ns
37 ns
CVCTV
CVDEX
CHCTV
CLLV
Control Active Delay 2
LOCK Valid/Invalid Delay
24
ETC [ ETC ]
