ST90158 - EXTERNAL MEMORY INTERFACE (EXTMI)
REGISTER DESCRIPTION (Cont’d)
EXTERNAL MEMORY REGISTER 2 (EMR2)
R246 - Read/Write
Register Page: 21
the contents of ISR. In this case, iretwill also
restore CSR from the stack. This approach al-
lows interrupt service routines to access the en-
tire 4 Mbytes of address space. The drawback is
that the interrupt response time is slightly in-
creased, because of the need to also save CSR
on the stack. Full compatibility with the original
ST9 is lost in this case, because the interrupt
stack frame is different.
Reset value: 0001 1111 (1Fh)
7
0
MEM
-
ENCSR DPRREM
LAS1 LAS0 UAS1 UAS0
SEL
Bit 7 = Reserved.
Bit 5 = DPRREM: Data Page Registers remapping
0: The locations of the four MMU (Memory Man-
agement Unit) Data Page Registers (DPR0,
DPR1, DPR2 and DPR3) are in page 21.
1: The four MMU Data Page Registers are
swapped with that of the Data Registers of ports
0-3.
Bit 6 = ENCSR: Enable Code Segment Register.
This bit affects the ST9 CPU behavior whenever
an interrupt request is issued.
0: For the duration of the interrupt service routine,
ISR is used instead of CSR, and only the PC
and Flags are pushed. This avoids saving the
CSR on the stack in the event of an interrupt,
thus ensuring a faster interrupt response time. It
is not possible for an interrupt service routine to
perform inter-segment calls or jumps: these in-
structions would update the CSR, which, in this
case, is not used (ISR is used instead). The
code segment size for all interrupt service rou-
tines is thus limited to 64K bytes. This mode en-
sures compatibiliy with the original ST9.
1:If ENCSR is set, ISR is only used to point to the
interrupt vector table and to initialize the CSR at
the beginning of the interrupt service routine: the
old CSR is pushed onto the stack together with
the PC and flags, and CSR is then loaded with
Refer to Figure 43
Bit 4 = MEMSEL: Memory Selection.
Warning: Must be kept at 1.
Bit 3:2 = LAS[1:0]: Lower memory address strobe
stretch.
These two bits contain the number of wait cycles
(from 0 to 3) to add to the System Clock to stretch
AS during external lower memory block accesses
(MSB of 22-bit internal address=0). The reset val-
ue is 3.
87/199
9
ETC [ ETC ]
